SCLS951A August   2023  – November 2023 SN74LV8T165-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LVxT Enhanced Input Voltage
        1. 7.3.1.1 Down Translation
        2. 7.3.1.2 Up Translation
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Latching Logic with Known Power-Up State
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Specification Description Condition MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VIH(1) High-level input voltage VCC = 1.65 V to 2 V 1.1 V
VCC = 2.25 V to 2.75 V 1.28
VCC = 3 V to 3.6 V 1.45
VCC = 4.5 V to 5.5 V 2
VIL(1) Low-Level input voltage VCC = 1.65 V to 2 V 0.51 V
VCC = 2.25 V to 2.75 V 0.65
VCC = 3 V to 3.6 V 0.75
VCC = 4.5 V to 5.5 V 0.8
IO Output current VCC = 1.6 V to 2 V ±8 mA
VCC = 2.25 V to 2.75 V ±15
VCC = 3.3 V to 5.0 V ±25
Δt/Δv Input transition rise or fall rate VCC = 1.6 V to 5.0 V 20 ns/V
Δt/ΔVCC(2) Safe supply ramp rate for POR VCC = 1.6 V to 5.5 V 6 µs/V
TA Operating free-air temperature -40 125 °C
(1) All inputs of the device must be held at a valid high or low state for proper device operation. Refer to the Feature Description section under LVxT Enhanced Input Voltage for details.
(2) VCC must start ramping below VPOR(min) and reach above VPOR(max) to allow proper reset functionality. Refer to Electrical Characteristics for details.