SCLS951A August   2023  – November 2023 SN74LV8T165-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LVxT Enhanced Input Voltage
        1. 7.3.1.1 Down Translation
        2. 7.3.1.2 Up Translation
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Latching Logic with Known Power-Up State
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TA = 25°C -40°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX
VOH IOH = -50 µA 1.65 V to 5.5 V VCC-0.1 VCC-0.1 V
IOH = -2 mA 1.65 V to 2 V 1.28 1.7 (1) 1.21
IOH = -3 mA 2.25 V to 2.75 V 2 2.4(1) 1.93
IOH = -5.5 mA 3 V to 3.6 V 2.6 3.08(1) 2.49
IOH = -8 mA 4.5 V to 5.5 V 4.1 4.65(1) 3.95
VOL IOL = 50 µA 1.65 V to 5.5 V 0.1 0.1 V
IOL = 2 mA 1.65 V to 2 V 0.1(1) 0.2 0.25
IOL = 3 mA 2.25 V to 2.75 V 0.1(1) 0.15 0.2
IOL = 5.5 mA 3 V to 3.6 V 0.2(1) 0.2 0.25
IOL = 8 mA 4.5 V to 5.5 V 0.3(1) 0.3 0.35
II VI = 0 V or VCC 0 V to 5.5 V ±0.1 ±1 µA
ICC VI = 0 V or VCC, IO = 0; open on loading 1.65 V to 5.5 V 2 20 µA
ΔICC One input at 0.3 V or 3.4 V, other inputs at 0 or VCC, IO = 0 5.5 V 1.35 1.5 mA
One input at 0.3 V or 1.1 V, other inputs at 0 or VCC, IO = 0 1.8 V 10 20 µA
CI VI = VCC or GND 5 V 4 10 10 pF
CPD(2)(3) No load, F = 1 MHz 5 V 32 pF
VPOR VCC ramp rate of 6 µs/V to 100 ms/V 1.65 V to 5.5 V 0.3 1.5 0.3 1.5 V
(1) Typical value at nearest nominal voltage (1.8 V, 2.5 V, 3.3 V, and 5 V)
(2) CPD is used to determine the dynamic power consumption, per channel.
(3) PD= VCC2 × FI × (CPD + CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage.