SCLS908A December   2022  – April 2023 SN74LV8T245-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics - 1.8-V VCC
    7. 6.7  Switching Characteristics - 2.5-V VCC
    8. 6.8  Switching Characteristics - 3.3-V VCC
    9. 6.9  Switching Characteristics - 5-V VCC
    10. 6.10 Noise Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS 3-State Outputs
      2. 8.3.2 Clamp Diode Structure
      3. 8.3.3 LVxT Enhanced Input Voltage
        1. 8.3.3.1 Down Translation
        2. 8.3.3.2 Up Translation
      4. 8.3.4 Wettable Flanks
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
      1. 9.3.1 Power Considerations
      2. 9.3.2 Input Considerations
      3. 9.3.3 Output Considerations
      4. 9.3.4 Detailed Design Procedure
    4. 9.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74LV8T245-Q1 is an octal bus transceiver with 3-state outputs. All eight channels are controlled by the direction (DIR) pin and output enable (OE) pin. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

Package Information(1)
PART NUMBERPACKAGEBODY SIZE (NOM)
SN74LV8T245-Q1 RKS (VQFN, 20) 4.50 mm × 2.50 mm
DGS (VSSOP, 20) 5.10 mm × 3.00 mm
PW (TSSOP, 20) 6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20210714-CA0I-BVBH-1VWX-ZHJZJR8CL0TQ-low.gif Simplified Logic Diagram (Positive Logic)