SCLS902 February   2024 SN74LV8T594

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Feature Description
    1. 8.1 Balanced CMOS Push-Pull Outputs
    2. 8.2 Latching Logic with Known Power-Up State
    3. 8.3 LVxT Enhanced Input Voltage
    4. 8.4 Clamp Diode Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
tH Hold time SER after SRCLK↑ 1.8V 0 0 0 ns
tSU Setup time SER before SRCLK↑ 1.8V 7.9 9.8 9.8 ns
SRCLK↑ before RCLK↑ 1.8V 8.1 10.1 10.1 ns
SRCLR high (inactive) before SRCLK↑ 1.8V 2.2 3 3 ns
SRCLR low before RCLK↑ 1.8V 8.9 11.2 11.2 ns
tW Pulse duration RCLK or SRCLK high or low 1.8V 5.9 7 7 ns
RCLR or SRCLR low 1.8V 6.5 8.3 8.3 ns
tH Hold time SER after SRCLK↑ 2.5V 0 0 0 ns
tSU Setup time SER before SRCLK↑ 2.5V 4.6 5.9 5.9 ns
SRCLK↑ before RCLK↑ 2.5V 3.9 5.3 5.3 ns
SRCLR high (inactive) before SRCLK↑ 2.5V 1.1 1.7 1.7 ns
SRCLR low before RCLK↑ 2.5V 5.1 6.6 6.6 ns
tW Pulse duration RCLK or SRCLK high or low 2.5V 4.3 4.3 4.3 ns
RCLR or SRCLR low 2.5V 4.3 5.2 5.2 ns
tH Hold time SER after SRCLK↑ 3.3V 0 0 0 ns
tSU Setup time SER before SRCLK↑ 3.3V 3.2 4 4 ns
SRCLK↑ before RCLK↑ 3.3V 2.5 3.2 3.2 ns
SRCLR high (inactive) before SRCLK↑ 3.3V 0.7 1 1 ns
SRCLR low before RCLK↑ 3.3V 3.6 4.5 4.5 ns
tW Pulse duration RCLK or SRCLK high or low 3.3V 4.3 4.3 4.3 ns
RCLR or SRCLR low 3.3V 4.3 4.3 4.3 ns
tH Hold time SER after SRCLK↑ 5V 0 0 0 ns
tSU Setup time SER before SRCLK↑ 5V 1.3 1.8 1.8 ns
SRCLK↑ before RCLK↑ 5V 1.6 2.1 2.1 ns
SRCLR high (inactive) before SRCLK↑ 5V 0.5 0.7 0.7 ns
SRCLR low before RCLK↑ 5V 1.6 2.1 2.1 ns
tW Pulse duration RCLK or SRCLK high or low 5V 4.3 4.3 4.3 ns
RCLR or SRCLR low 5V 4.3 4.3 4.3 ns