SCAS280S January   1993  – May 2024 SN54LVC02A , SN74LVC02A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Description
  4. 3 Pin Configuration and Functions
  5. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions, SN54LVC02A
    4. 4.4  Recommended Operating Conditions, SN74LVC02A
    5. 4.5  Thermal Information
    6. 4.6  Electrical Characteristics, SN54LVC02A
    7. 4.7  Electrical Characteristics, SN74LVC02A
    8. 4.8  Switching Characteristics, SN54LVC02A
    9. 4.9  Switching Characteristics, SN74LVC02A
    10. 4.10 Operating Characteristics
  6. 5 Parameter Measurement Information
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagram
    2. 6.2 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Power Supply Recommendations
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • PW|14
  • BQA|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment.

The device performs the Boolean function Y = A + B or Y = A ⋅ B in positive logic.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

Device Information
PART NUMBER PACKAGE SIZE(1) PACKAGE SIZE(2) BODY SIZE(3)
SNx4LVC02A BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm
D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.9mm
DB (SSOP, 14) 6.2mm × 7.8mm 6.2mm × 5.3mm
NS (SOP, 14) 10.2mm × 7.8mm 10.3mm × 5.3mm
PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.4mm
RGY (VQFN, 14) 3.5mm × 3.5mm 3.5mm × 3.5mm
FK (LCCC, 20) 8.9mm x 8.9mm 8.89mm × 8.89mm
J (CDIP, 14) 19.55mm x 7.9mm 19.55mm x 6.7mm
W (CFP, 14) 9.21mm x 9mm 9.21mm x 6.28mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
SN54LVC02A SN74LVC02A Logic Diagram, Each Gate (Positive Logic) Logic Diagram, Each Gate (Positive Logic)