SCAS339U March   1994  – July 2024 SN74LVC126A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Thermal Information

THERMAL METRIC(1) SN74LVC126A UNIT
BQA (WQFN) D (SOIC) DB (SSOP) DGV (TVSOP) NS (SOP) PW (TSSOP) RGY (VQFN)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 102.3(3) 127.8(2) 112.2(2) 140.9(2) 123.8(2) 150.8(2) 92.1(3) °C/W
RθJC(top) Junction-to-case (top) thermal resistance 96.8 81.9 64.2 59.9 51.7 78.3 91.8 °C/W
RθJB Junction-to-board thermal resistance 70.9 84.4 59.6 70.2 52.7 93.8 66.7 °C/W
ψJT Junction-to-top characterization parameter 16.6 39.6 28.3 9.1 20.7 38.2 20 °C/W
ψJB Junction-to-board characterization parameter 70.9 83.9 59.1 69.5 52.3 93.2 66.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 50.1 N/A N/A N/A N/A N/A 50.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.