SCLSA17 May   2024 SN74LVC165A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
    10. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Latching Logic
      4. 7.3.4 Partial Power Down (Ioff)
      5. 7.3.5 Standard CMOS Inputs
      6. 7.3.6 Wettable Flanks
      7. 7.3.7 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • BQB|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE (NOM)(3)
SN74LVC165A-Q1 BQB (WQFN, 16) 3.5mm × 2.5mm 3.5mm × 2.5mm
D (SOIC, 16) 9.9mm × 6mm 9.9mm × 3.9mm
PW (TSSOP, 16) 5mm × 6.4mm 5mm × 4.4mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable
(3) The body size (length × width) is a nominal value and does not include pins.
SN74LVC165A-Q1 Functional Diagram Functional Diagram