SCLSA15 May   2024 SN74LVC166A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
    10. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Partial Power Down (Ioff)
      4. 7.3.4 Standard CMOS Inputs
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
Fclock Clock frequency 1.2 V ± 0.1 V 59 MHz
1.5 V ± 0.15 V 64 MHz
1.8 V ± 0.15 V 64 MHz
2.5 V ± 0.2 V 100 MHz
3.3 V ± 0.3 V 104 MHz
tW Pulse duration CLR low 1.2 V ± 0.1 V 6.9 ns
tW Pulse duration SH/LD low 1.2 V ± 0.1 V 6.9 ns
tW Pulse duration CLK 1.2 V ± 0.1 V 7 ns
tSU Setup time SH/LD high before CLK↑ 1.2 V ± 0.1 V 16.5 ns
tSU Setup time SER before CLK↑ 1.2 V ± 0.1 V 10.1 ns
tSU Setup time CLK INH before CLK↑ 1.2 V ± 0.1 V 1 ns
tSU Setup time Data before CLK↑ 1.2 V ± 0.1 V 10 ns
tSU Setup time CLR inactive before CLK↑ 1.2 V ± 0.1 V 10.1 ns
tH Hold time SER data after CLK↑ 1.2 V ± 0.1 V 0.4 ns
tH Hold time Parallel data after SH/LD↓ 1.2 V ± 0.1 V 1.8 ns
tH Hold time SH/LD high after CLK↑ 1.2 V ± 0.1 V 0 ns
tH Hold time CLK INH high after CLK↑ 1.2 V ± 0.1 V 0.4 ns
tH Hold time Data after CLK↑ 1.2 V ± 0.1 V 1 ns
tW Pulse duration CLR low 1.5 V ± 0.15 V 6.9 ns
tW Pulse duration SH/LD low 1.5 V ± 0.15 V 6.9 ns
tW Pulse duration CLK 1.5 V ± 0.15 V 7 ns
tSU Setup time SH/LD high before CLK↑ 1.5 V ± 0.15 V 10 ns
tSU Setup time SER before CLK↑ 1.5 V ± 0.15 V 10.1 ns
tSU Setup time CLK INH before CLK↑ 1.5 V ± 0.15 V 1 ns
tSU Setup time Data before CLK↑ 1.5 V ± 0.15 V 10 ns
tSU Setup time CLR inactive before CLK↑ 1.5 V ± 0.15 V 10.1 ns
tH Hold time SER data after CLK↑ 1.5 V ± 0.15 V 1.2 ns
tH Hold time Parallel data after SH/LD↓ 1.5 V ± 0.15 V 1.9 ns
tH Hold time SH/LD high after CLK↑ 1.5 V ± 0.15 V 1 ns
tH Hold time CLK INH high after CLK↑ 1.5 V ± 0.15 V 0.6 ns
tH Hold time Data after CLK↑ 1.5 V ± 0.15 V 1.8 ns
tW Pulse duration CLR low 1.8 V ± 0.15 V 6.9 ns
tW Pulse duration SH/LD low 1.8 V ± 0.15 V 6.9 ns
tW Pulse duration CLK 1.8 V ± 0.15 V 7 ns
tSU Setup time SH/LD high before CLK↑ 1.8 V ± 0.15 V 8 ns
tSU Setup time SER before CLK↑ 1.8 V ± 0.15 V 10.1 ns
tSU Setup time CLK INH before CLK↑ 1.8 V ± 0.15 V 1 ns
tSU Setup time Data before CLK↑ 1.8 V ± 0.15 V 8 ns
tSU Setup time CLR inactive before CLK↑ 1.8 V ± 0.15 V 10.1 ns
tH Hold time SER data after CLK↑ 1.8 V ± 0.15 V 0.2 ns
tH Hold time Parallel data after SH/LD↓ 1.8 V ± 0.15 V 0.8 ns
tH Hold time SH/LD high after CLK↑ 1.8 V ± 0.15 V 0 ns
tH Hold time CLK INH high after CLK↑ 1.8 V ± 0.15 V 0.3 ns
tH Hold time Data after CLK↑ 1.8 V ± 0.15 V 1 ns
tW Pulse duration CLR low 2.5 V ± 0.2 V 5.4 ns
tW Pulse duration SH/LD low 2.5 V ± 0.2 V 5.4 ns
tW Pulse duration CLK 2.5 V ± 0.2 V 4.5 ns
tSU Setup time SH/LD high before CLK↑ 2.5 V ± 0.2 V 4.5 ns
tSU Setup time SER before CLK↑ 2.5 V ± 0.2 V 5.9 ns
tSU Setup time CLK INH before CLK↑ 2.5 V ± 0.2 V 1 ns
tSU Setup time Data before CLK↑ 2.5 V ± 0.2 V 4.5 ns
tSU Setup time CLR inactive before CLK↑ 2.5 V ± 0.2 V 5.9 ns
tH Hold time SER data after CLK↑ 2.5 V ± 0.2 V 0.5 ns
tH Hold time Parallel data after SH/LD↓ 2.5 V ± 0.2 V 0 ns
tH Hold time SH/LD high after CLK↑ 2.5 V ± 0.2 V 0.1 ns
tH Hold time CLK INH high after CLK↑ 2.5 V ± 0.2 V 0.3 ns
tH Hold time Data after CLK↑ 2.5 V ± 0.2 V 1.5 ns
tW Pulse duration CLR low 3.3 V ± 0.3 V 4.3 ns
tW Pulse duration SH/LD low 3.3 V ± 0.3 V 4.3 ns
tW Pulse duration CLK 3.3 V ± 0.3 V 4.3 ns
tSU Setup time SH/LD high before CLK↑ 3.3 V ± 0.3 V 3.5 ns
tSU Setup time SER before CLK↑ 3.3 V ± 0.3 V 4 ns
tSU Setup time CLK INH before CLK↑ 3.3 V ± 0.3 V 1 ns
tSU Setup time Data before CLK↑ 3.3 V ± 0.3 V 2.9 ns
tSU Setup time CLR inactive before CLK↑ 3.3 V ± 0.3 V 4 ns
tH Hold time SER data after CLK↑ 3.3 V ± 0.3 V 0.5 ns
tH Hold time Parallel data after SH/LD↓ 3.3 V ± 0.3 V 0 ns
tH Hold time SH/LD high after CLK↑ 3.3 V ± 0.3 V 0.2 ns
tH Hold time CLK INH high after CLK↑ 3.3 V ± 0.3 V 0.5 ns
tH Hold time Data after CLK↑ 3.3 V ± 0.3 V 1.5 ns