SCES487I September   2003  – November 2024 SN74LVC1G11

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics, CL = 15 pF
    7. 5.7  Switching Characteristics, CL = 30 pF or 50 pF
    8. 5.8  Switching Characteristics, CL = 30 pF or 50 pF
    9. 5.9  Operating Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support (Analog)
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
  • DSF|6
  • YZP|6
  • DCK|6
  • DRY|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

This 3-input AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G11 device features a three-input AND gate. The output state is determined by eight patterns of 3-bit input. All inputs can be connected to VCC or GND.

This device is fully-specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.