SCES586E July   2004  – March 2024 SN74LVC1G123

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics, CL = 15 pF, –40°C to 85°C
    8. 5.8  Switching Characteristics, CL = 50 pF, –40°C to 85°C
    9. 5.9  Switching Characteristics, CL = 50 pF, –40°C to 125°C
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Feature Description

This part is available in the Texas Instruments NanoFree™ package. It supports 5-V VCC operation and accepts inputs up to 5.5 V. The max tpd is 8 ns at 3.3 V. It supports mixed-mode voltage operation on all ports.

Down translation can be achieved to VCC from up to 5.5 V.

Schmitt-trigger circuitry on A and B inputs allows for slow input transition rates. The device can be edge triggered from active-high or active-low gated logic inputs. It can support up to 100% duty cycle from retriggering.

Clear can be used to terminate the output pulse early.

Glitch-free power-up reset is on all outputs.

Ioff supports live insertion, partial-power-down mode, and back-drive protection.

Latch-up performance exceeds 100 mA per JESD 78, Class II.