SCLSA29 October   2024 SN74LVC1G16

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Noise Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Feature Description
      1. 7.1.1 Open-Drain CMOS Outputs
      2. 7.1.2 CMOS Schmitt-Trigger Inputs
      3. 7.1.3 Clamp Diode Structure
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns.

The outputs are measured individually with one input transition per measurement.

TEST S1 RL CL ΔV VLOAD
tPLZ, tPZL CLOSED 500Ω 50pF 0.3V 2×VCC
VCC Vt RL CL ΔV VLOAD
1.2V ± 0.1V VCC/2 2kΩ 15pF 0.1V 2×VCC
1.5V ± 0.12V VCC/2 2kΩ 15pF 0.1V 2×VCC
1.8V ± 0.15V VCC/2 1kΩ 15pF/30pF 0.15V 2×VCC
2.5V ± 0.2V VCC/2 500Ω 15pF/30pF 0.15V 2×VCC
3.3V ± 0.3V 1.5V 500Ω 15pF/50pF 0.3V 6V
5.0V ± 0.5V 1.5V 500Ω 15pF/50pF 0.3V 6V

SN74LVC1G16 Load Circuit for Open-Drain Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Open-Drain Outputs
SN74LVC1G16 Voltage Waveforms Propagation Delays
(1) tPLZ is the same as tdis.
(2) tPZL is the same as ten.
Figure 6-2 Voltage Waveforms Propagation Delays