SCES538G January 2004 – February 2020 SN74LVC1G38
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The SN74LVC1G38 device is designed for 1.65-V to 5.5-V VCC operation.
This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A × B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
DEVICE NAME | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN74LVC1G38DBV | SOT-23 (5) | 2.90 mm × 1.60 mm |
SN74LVC1G38DCK | SC70 (5) | 2.00 mm × 1.25 mm |
SN74LVC1G38DRY | SON (6) | 1.45 mm × 1.00 mm |
SN74LVC1G38DSF | SON (6) | 1.00 mm × 1.00 mm |
SN74LVC1G38YZP | DSBGA (5) | 0.89 mm × 1.39 mm |
SN74LVC1G38DPW | X2SON (5) | 0.80 mm × 0.80 mm |