SCES220U April   1999  – April 2017 SN74LVC1G79

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: TA = -40°C to +85°C
    7. 6.7  Timing Requirements: TA = -40°C to +125°C
    8. 6.8  Switching Characteristics: CL = 15 pF, TA = -40°C to +85°C
    9. 6.9  Switching Characteristics: CL = 30 or 50 pF, TA = -40°C to +85°C
    10. 6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA = -40°C to +125°C
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • DCK|5
  • DRL|5
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

A useful application for the SN74LVC1G79 is using it as a data latch with low-voltage data retention. This application implements the use of a microcontroller GPIO pin to act as a clock to set the output state and a second GPIO to provide the input data. If the SN74LVC1G79 is being powered from 1.8 V and there is concern that a power glitch could exist as low as 1.5 V, the device will retain the state of the Q output. An example of this data retention is shown in Figure 8 where the VCC drops to 1.5 V and the Q output maintains the HIGH output state when VCC returns to 1.8 V. If the VCC voltage drops below 1.5 V, data retention is not guaranteed.

9.2 Typical Application

SN74LVC1G79 SN74LVC1G79-Application.gif Figure 7. Low Voltage Data Retention With SN74LVC1G79

9.2.1 Design Requirements

The SN74LVC1G79 device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.

9.2.2 Detailed Design Procedure

  1. Recommended input conditions:
  2. Recommended output conditions:

9.2.3 Application Curve

SN74LVC1G79 DataRetentionWithVCCGlitch.gif Figure 8. Data Retention With VCC Glitch Down to 1.5 V