SCES885
April 2017
SN74LVC1G80-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements: TA = -40°C to +85°C
6.7
Timing Requirements: TA = -40°C to +125°C
6.8
Switching Characteristics: TA = -40°C to +85°C, CL = 15 pF
6.9
Switching Characteristics: TA = -40°C to +85°C, CL = 30 pF or 50 pF
6.10
Switching Characteristics: TA = -40°C to +125°C, CL = 30 pF or 50 pF
6.11
Operating Characteristics
6.12
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced High-Drive CMOS Push-Pull Outputs
8.3.2
Standard CMOS Inputs
8.3.3
Clamp Diodes
8.3.4
Partial Power Down (Ioff)
8.3.5
Over-Voltage Tolerant Inputs
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DCK|5
MPDS025J
Thermal pad, mechanical data (Package|Pins)
Orderable Information
sces885_oa
sces885_pm
5
Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
Pin Functions
(1)
PIN
I/O
DESCRIPTION
NO.
NAME
1
D
I
Data input
2
CLK
I
Positive-Edge-Triggered Clock input
3
GND
—
Ground pin
4
Q
O
Inverted output
5
V
CC
—
Positive Supply
(1)
See
Mechanical, Packaging, and Orderable Information
for dimensions