SCES515N December   2003  – June 2024 SN74LVC1T45

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics (VCCA = 1.8V ± 0.15V)
    7. 5.7  Switching Characteristics (VCCA = 2.5V ± 0.2V)
    8. 5.8  Switching Characteristics (VCCA = 3.3V ± 0.3V)
    9. 5.9  Switching Characteristics (VCCA = 5V ±0.5V)
    10. 5.10 Operating Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65V to 5.5V Power-Supply Range
      2. 7.3.2 Support High Speed Translation
      3. 7.3.3 Ioff Supports Partial Power-Down Mode Operation
      4. 7.3.4 Balanced High-Drive CMOS Push-Pull Outputs
      5. 7.3.5 Glitch-Free Power Supply Sequencing
      6. 7.3.6 Vcc Isolation
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Unidirectional Logic Level-Shifting Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Bidirectional Logic Level-Shifting Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Enable Times
        3. 8.2.2.3 Application Curve
    3.     42
    4. 8.3 Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.2.2.1 Enable Times

Calculate the enable times for the SN74LVC1T45 using the following formulas:

  • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
  • tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
  • tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
  • tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.