SCLS975A October   2023  – April 2024 SN74LVC2G100-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Noise Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CMOS Schmitt-Trigger Inputs
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Clamp Diode Structure
      4. 7.3.4 Wettable Flanks
    4. 7.4 Device Functional Modes
    5. 7.5 Combinatorial Logic Configurations
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20230913-CA0I-F8L1-9QQ5-S8VF6DK0SXM1-low.svgFigure 4-1 BQB Package,16-Pin WQFN(Top View)
GUID-20230913-CA0I-P7PV-L7JN-1RZZKH96KQSH-low.svgFigure 4-2 PW Package,16-Pin TSSOP (Preview)(Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
CLR11IClear for Channel 1, active low
DA12IChannel 1, Input A
DB13IChannel 1, Input B
DC14IChannel 1, Input C
DD15IChannel 1, Input D
Q16OChannel 1, Output Q
CLK1 7 I Clock for Channel 1, rising edge triggered
GND8GGround
CLK29IClock for Channel 2, rising edge triggered
Q210OChannel 2, Output Q
DD211IChannel 2, Input D
DC212IChannel 2, Input C
DB213IChannel 2, Input B
DA214IChannel 2, Input A
CLR2 15 I Clear for Channel 2, active low
VCC16PPositive Supply
Thermal Pad(2) — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
(2) BQB package only