SCLSA10 April   2024 SN74LVC2G100

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Noise Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CMOS Schmitt-Trigger Inputs
      2. 7.3.2 Balanced CMOS Push-Pull Outputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
    5. 7.5 Combinatorial Logic Configurations
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN TYP MAX
fclock Clock frequency 1.2V ± 0.1V 10 MHz
1.5V ± 0.15 V 44
1.8V ± 0.15 V 73 MHz
2.5V ± 0.2V 150
3.3V ± 0.3V 150
tW Pulse duration CLR low 1.2V ± 0.1V 4.3 ns
1.5V ± 0.15 V 1.6
1.8V ± 0.15 V 4.1
2.5 ± 0.2V 3.3
3.3V ± 0.3V 3.3
CLK 1.2V ± 0.1V 6.95
1.5V ± 0.15 V 2.75
1.8V ± 0.15 V 4.1
2.5 ± 0.2V 3.3
3.3V ± 0.3V 3.3
tSU Setup time before CLK↑ DAx, DBx and DCx   1.2V ± 0.1V 26.4 ns
1.5V ± 0.15 V 12.8
1.8V ± 0.15 V 8.34
2.5 ± 0.2V 6.03
3.3V ± 0.3V 6.03
DDx   1.2V ± 0.1V 20.3 ns
1.5V ± 0.15 V 10.793
1.8V ± 0.15 V 6.66
2.5 ± 0.2V 4.824
3.3V ± 0.3V 4.824
CLR Inactive 1.2V ± 0.1V 11.6 ns
1.5V ± 0.15 V 8.79
1.8V ± 0.15 V 4.34
2.5 ± 0.2V 2.51
3.3V ± 0.3V 2.324
tH Hold time, data after CLK↑ DAx, DBx and DCx 1.2V ± 0.1V 0 ns
1.5V ± 0.15 V 0
1.8 ± 0.15 V 1
2.5 ± 0.2V 1
3.3 ± 0.3V 1
DDx  1.2V ± 0.1V 0
1.5V ± 0.15 V 0
1.8V ± 0.15 V 0.7
2.5V ± 0.2V 0.7
3.3V ± 0.3V 0.7