SCLSA09 June   2024 SN74LVC2G101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Noise Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Latching Logic
      4. 7.3.4 Partial Power Down (Ioff)
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt ≤ 2.5ns.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured individually with one input transition per measurement.

VCC Vt RL CL ΔV
1.2V ± 0.1V VCC/2 2kΩ 15pF 0.1V
1.5V ± 0.12V VCC/2 2kΩ 15pF 0.1V
1.8V ± 0.15V VCC/2 1kΩ 30pF 0.15V
2.5V ± 0.2V VCC/2 500Ω 30pF 0.15V
2.7V 1.5V 500Ω 50pF 0.3V
3.3V ± 0.3V 1.5V 500Ω 50pF 0.3V

SN74LVC2G101 Load Circuit for Push-Pull Outputs
(1) CL includes probe and test-fixture capacitance.
Figure 6-1 Load Circuit for Push-Pull Outputs
SN74LVC2G101 Voltage Waveforms, Setup and Hold TimesFigure 6-3 Voltage Waveforms, Setup and Hold Times
SN74LVC2G101 Voltage Waveforms, Input and Output Transition Times
(1) The greater between tr and tf is the same as tt.
Figure 6-5 Voltage Waveforms, Input and Output Transition Times
SN74LVC2G101 Voltage Waveforms, Pulse DurationFigure 6-2 Voltage Waveforms, Pulse Duration
SN74LVC2G101 Voltage Waveforms Propagation Delays
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4 Voltage Waveforms Propagation Delays
SN74LVC2G101 Voltage Waveforms, Noise
Noise values measured with all other outputs simultaneously switching.
Figure 6-6 Voltage Waveforms, Noise