SCLSA09 June   2024 SN74LVC2G101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Noise Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Latching Logic
      4. 7.3.4 Partial Power Down (Ioff)
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT
MIN MAX
fclock Clock frequency 1.2V ± 0.1V 10 MHz
1.5V ± 0.15V 40
fclock Clock frequency 1.8V ± 0.15V 70 MHz
2.5V ± 0.2V 150
3.3V ± 0.3V 160
tW Pulse duration CLR low 1.2V ± 0.1V 4.3 ns
1.5V ± 0.15V 1.6
CLK 1.2V ± 0.1V 7
1.5V ± 0.15V 2.8
tW Pulse duration CLR low 1.8V ± 0.15V 4.1 ns
2.5 ± 0.2V 3.3
3.3V ± 0.3V 3.3
CLK 1.8V ± 0.15V 4.1
2.5 ± 0.2V 3.3
3.3V ± 0.3V 3.3
tSU Setup time before CLK↑ D input pin relative to CLKx pins 1.2V ± 0.1V 3.9 ns
1.5V ± 0.15V 2.5
CLR Inactive 1.2V ± 0.1V 11.6
1.5V ± 0.15V 8.8
tSU Setup time before CLK↑ D input pin relative to CLKx pins 1.8V ± 0.15V 3.6 ns
2.5 ± 0.2V 2.3
3.3V ± 0.3V 2.3
CLR Inactive 1.8V ± 0.15V 4.3
2.5 ± 0.2V 2.5
3.3V ± 0.3V 2.3
tCLKA_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 1.2V ± 0.1V 21 ns
tCLKA_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 1.5V ± 0.15V 9.7 ns
tCLKA_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 1.8V ± 0.15V 21 ns
tCLKA_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 2.5V ± 0.2V 9.8 ns
tCLKA_SU Set up time between CLKx inputs CLKA input pin relative to CLKB, CLKC and CLKD pins 3.3V ± 0.3V 21 ns
tCLKB_SU Set up time between CLKx inputs CLKB input pin relative to CLKA, CLKC and CLKD pins 1.2V ± 0.1V 9.8 ns
tCLKB_SU Set up time between CLKx inputs CLKB input pin relative to CLKA, CLKC and CLKD pins 1.5V ± 0.15V 15 ns
tCLKB_SU Set up time between CLKx inputs CLKB input pin relative to CLKA, CLKC and CLKD pins 1.8V ± 0.15V 7.8 ns
tCLKB_SU Set up time between CLKx inputs CLKB input pin relative to CLKA, CLKC and CLKD pins 2.5V ± 0.2V 7 ns
tCLKB_SU Set up time between CLKx inputs CLKB input pin relative to CLKA, CLKC and CLKD pins 3.3V ± 0.3V 5.1 ns
tCLKC_SU Set up time between CLKx inputs CLKC input pin relative to CLKA, CLKB and CLKD pins 1.2V ± 0.1V 5.1 ns
tCLKC_SU Set up time between CLKx inputs CLKC input pin relative to CLKA, CLKB and CLKD pins 1.5V ± 0.15V 7 ns
tCLKC_SU Set up time between CLKx inputs CLKC input pin relative to CLKA, CLKB and CLKD pins 1.8V ± 0.15V 5 ns
tCLKC_SU Set up time between CLKx inputs CLKC input pin relative to CLKA, CLKB and CLKD pins 2.5V ± 0.2V 5 ns
tCLKC_SU Set up time between CLKx inputs CLKC input pin relative to CLKA, CLKB and CLKD pins 3.3V ± 0.3V 7 ns
tCLKD_SU Set up time between CLKx inputs CLKD input pin relative to CLKA, CLKB and CLKC pins 1.2V ± 0.1V 5 ns
tCLKD_SU Set up time between CLKx inputs CLKD input pin relative to CLKA, CLKB and CLKC pins 1.5V ± 0.15V 5 ns
tCLKD_SU Set up time between CLKx inputs CLKD input pin relative to CLKA, CLKB and CLKC pins 1.8V ± 0.15V 5.4 ns
tCLKD_SU Set up time between CLKx inputs CLKD input pin relative to CLKA, CLKB and CLKC pins 2.5V ± 0.2V 3.9 ns
tCLKD_SU Set up time between CLKx inputs CLKD input pin relative to CLKA, CLKB and CLKC pins 3.3V ± 0.3V 3.9 ns
tH Hold time, data after CLK↑ D input pin relative to CLKx pins 1.2V ± 0.1V 10 ns
1.5V ± 0.15V 4
tH Hold time, data after CLK↑ D input pin relative to CLKx pins 1.8V ± 0.15V 2.8 ns
2.5 ± 0.2V 2.3
3.3 ± 0.3V 2.3