SCES200O April   1999  – August 2015 SN74LVC2G14

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics, -40°C to 85°C
    7. 6.7 Switching Characteristics, -40°C to 125°C
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Support Translation Down (5 V to 3.3 V; 3.3 V to 1.8 V)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
  • YZP|6
  • DCK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Available in the TI NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.4 ns at 3.3 V
  • Low-Power Consumption, 10-μA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Support Translation Down
    (5 V to 3.3 V; 3.3 V to 1.8 V)
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II

2 Applications

  • Body Control Modules
  • Engine Control Modules
  • Arcade, Casino, and Gambling Machines
  • Servers and High-Performance Computing
  • EPOS, ECR, and Cash Drawer
  • Routers
  • Desktop PC

3 Description

This dual Schmitt-trigger inverter is designed for
1.65-V to 5.5-V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC2G14 device contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC2G14DBV SOT-23 (6) 2.90 mm × 1.60 mm
SN74LVC2G14DCK SC70 (6) 2.00 mm × 1.25 mm
SN74LVC2G14YZP DSBGA (6) 1.41 mm × 0.91 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

SN74LVC2G14 LD_CES200.gif