SCES203Q April   1999  – September 2021 SN74LVC2G74

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements, –40°C to +85°C
    7. 6.7  Timing Requirements, –40°C to +125°C
    8. 6.8  Switching Characteristics, –40°C to +85°C
    9. 6.9  Switching Characteristics, –40°C to +125°C
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Power Button Circuit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCU|8
  • YZP|8
  • DCT|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Requirements, –40°C to +125°C

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETERFROMTO–40°C to +125°CUNIT
VCC = 1.8 V
± 0.15 V		VCC = 2.5 V
± 0.2 V		VCC = 3.3 V
± 0.3 V		VCC = 5 V
± 0.5 V
MINMAXMINMAXMINMAXMINMAX
fclock80120120140MHz
twCLK6.23.53.53.3ns
PRE or CLR low6.23.53.53.3
tsuData2.92.31.91.7ns
PRE or CLR inactive1.921.81.6
th00.30.50.5ns