SCAS319J November   1993  – December 2014 SN74LVCH16652A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, 40°C to 85°C
    7. 7.7  Timing Requirements, 40°C to 125°C
    8. 7.8  Switching Characteristics, 40°C to 85°C
    9. 7.9  Switching Characteristics, 40°C to 125°C
    10. 7.10 Operating Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGG|56
  • DL|56
  • DGV|56
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH16652A device consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

Complementary output-enable (OEAB and OEBA) inputs control the transceiver functions. Select-control (SAB and SBA) inputs select whether real-time or stored data is transferred. A low input level selects real-time data, and a high input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Figure 5 illustrates the four fundamental bus-management functions that can be performed with SN74LVCH16652A.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the levels on the select-control or output-enable inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last level configuration.

To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pull-up or pull-down resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE or DIR.

9.2 Functional Block Diagram

fbd_cas319.gifFigure 4. Logic Diagram (Positive Logic)

9.3 Feature Description

  • Wide operating voltage range
    • Operates from 1.65 V to 3.6 V
  • Allows down voltage translation
    • Inputs accept voltages to 5.5 V
  • Ioff feature
    • Allows voltages on the inputs and outputs when VCC is 0 V
  • Bus hold on data Inputs eliminates the need for external pull-up/pull-down resistors

9.4 Device Functional Modes

Table 1. Function Table

INPUTS DATA I/O(1) OPERATION OR FUNCTION
OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8
L H H or L H or L X X Input Input Isolation
L H ↑ ↑ X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified(2) Store A, hold B
H H ↑ ↑ X(2) X Input Output Store A in both registers
L X H or L ↑ X X Unspecified(2) Input Hold A, store B
L L ↑ ↑ X X(2) Output Input Store B in both registers
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus
H L H or L H or L H H Output Output Stored A data to B bus and
stored B data to A bus
(1) The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
(2) Select control = L; clocks can occur simultaneously.
Select control = H; clocks must be staggered to load both registers.