SCES943 August   2022 SN74LXC1T45-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    7. 6.7  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    8. 6.8  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    9. 6.9  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    10. 6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    11. 6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    12. 6.12 Switching Characteristics: Tsk, TMAX
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 8.3.1.1 I/O's with Integrated Dynamic Pull-Down Resistors
        2. 8.3.1.2 Control Inputs with Integrated Static Pull-Down Resistors
      2. 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3 Partial Power Down (Ioff)
      4. 8.3.4 VCC Isolation and VCC Disconnect (Ioff-float)
      5. 8.3.5 Over-Voltage Tolerant Inputs
      6. 8.3.6 Glitch-Free Power Supply Sequencing
      7. 8.3.7 Negative Clamping Diodes
      8. 8.3.8 Fully Configurable Dual-Rail Design
      9. 8.3.9 Supports High-Speed Translation
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Enable Times
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Regulatory Requirements
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.13 Operating Characteristics

TA = 25℃ (1)
PARAMETER Test Conditions Supply Voltage (VCCB = VCCA) UNIT
1.2 ± 0.1 V 1.5 ± 0.1 V 1.8 ± 0.15 V 2.5 ± 0.2 V 3.3 ± 0.3 V 5.0 ± 0.5 V
TYP TYP TYP TYP TYP TYP
CpdA (2) A to B A Port
CL = 0, RL = Open
f = 10 MHz
trise = tfall = 1 ns		 3.2 3.4 3.5 3.7 3.9 5.1 pF
B to A 19.4 19.6 19.8 20.4 21.8 25.7
CpdB (2) A to B B Port
CL = 0, RL = Open
f = 10 MHz
trise = tfall = 1 ns		 19.3 19.5 19.7 20.4 21.6 25.3 pF
B to A 3.3 3.5 3.6 4.0 4.4 5.0
(1) For more information about power dissipation capacitance, see the CMOS Power Consumption and Cpd Calculation application report.
(2) CpdA and CpdB are repectively A-Port and B-Port power dissipation capacitances per transceiver.