SCES939 April   2022 SN74LXCH1T45

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    7. 6.7  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    8. 6.8  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    9. 6.9  Switching Characteristics, VCCA = 2.5 ± 0.2 V
    10. 6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    11. 6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    12. 6.12 Switching Characteristics: Tsk, TMAX
    13. 6.13 Operating Characteristics
    14. 6.14 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  CMOS Schmitt-Trigger Inputs
        1. 8.3.1.1 Control Inputs with Integrated Static Pull-Down Resistors
      2. 8.3.2  Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3  Partial Power Down (Ioff)
      4. 8.3.4  VCC Isolation and VCC Disconnect
      5. 8.3.5  Over-Voltage Tolerant Inputs
      6. 8.3.6  Glitch-Free Power Supply Sequencing
      7. 8.3.7  Negative Clamping Diodes
      8. 8.3.8  Fully Configurable Dual-Rail Design
      9. 8.3.9  Supports High-Speed Translation
      10. 8.3.10 Bus-Hold Data Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Enable Times
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2 Enable Times

Calculate the enable times for the SN74LXCH1T45 using the following formulas:

Equation 1. tA_en (DIR to A) = tdis (DIR to B) + tpd (B to A)
Equation 2. tB_en (DIR to B) = tdis (DIR to A) + tpd (A to B)

In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is switched until an output is expected. For example, if the SN74LXCH1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled (tdis) before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay (tpd). To avoid bus contention, care should be taken to not apply an input signal prior to the output being disabled (tdis maximum).