The SNx4LS24x, SNx4S24x octal buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The designer has a choice of selected combinations of inverting and non-inverting outputs, symmetrical, active-low output-control (G) inputs, and complementary output-control (G and G) inputs. These devices feature high fan-out, improved fan-in, and 400-mV noise margin. The SN74LS24x and SN74S24x devices can be used to drive terminated lines down to 133 Ω.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SN54LS24x, SN54S24x |
CDIP (20) – J | 24.20 mm × 6.92 mm |
CFP (20) – W | 7.02 mm × 13.72 mm | |
LCCC (20) – FK | 8.89 mm × 8.89 mm | |
SN74LS240, SN74LS244 |
SSOP (20) – DB | 7.20 mm × 5.30 mm |
SN74LS24x, SN74S24x |
SOIC (20) – DW | 12.80 mm × 7.50 mm |
PDIP (20) – N | 24.33 mm × 6.35 mm | |
SN74LS24x | SOP (20) – NS | 7.80 mm × 12.60 mm |
Changes from C Revision (May 2010) to D Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | 1G | I | Channel 1 output enable |
2 | 1A1 | I | Channel 1, A side 1 |
3 | 2Y4 | O | Channel 2, Y side 4 |
4 | 1A2 | I | Channel 1, A side 2 |
5 | 2Y3 | O | Channel 2, Y side 3 |
6 | 1A3 | I | Channel 1, A side 3 |
7 | 2Y2 | O | Channel 2, Y side 2 |
8 | 1A4 | I | Channel 1, A side 4 |
9 | 2Y1 | O | Channel 2, Y side 1 |
10 | GND | — | Ground |
11 | 2A1 | I | Channel 2, A side 1 |
12 | 1Y4 | O | Channel 1, Y side 4 |
13 | 2A2 | I | Channel 2, A side 2 |
14 | 1Y3 | O | Channel 1, Y side 3 |
15 | 2A3 | I | Channel 2, A side 3 |
16 | 1Y2 | O | Channel 1, Y side 2 |
17 | 2A4 | I | Channel 2, A side 4 |
18 | 1Y1 | O | Channel 1, Y side 1 |
19 | 2G/2G(1) | I | Channel 2 output enable |
20 | VCC | — | Power supply |