SCDS112E march   2001  â€“ september 2023 SN74TVC3306

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics (AC, VGATE = 3.3 V, Translating Down)
    7. 6.7  Switching Characteristics (AC, VGATE = 2.5 V, Translating Down)
    8. 6.8  Switching Characteristics (AC, VGATE = 3.3 V, Translating Up)
    9. 6.9  Switching Characteristics (AC, VGATE = 2.5 V, Translating Up)
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 Voltage Clamping
      2. 8.4.2 Voltage Passing
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Application Operating Conditions
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCU|8
  • DCT|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

For the clamping configuration, the common GATE input must be connected to one side (An or Bn) of any one of the pass transistors, making that the VBIAS connection of the reference transistor and the opposite side (Bn or An) the VREF connection. When VBIAS is connected through a 200-kΩ resistor to a 3-V to 5.5-V VCC supply and VREF is set to 0 V to VCC â€“ 0.6 V, the output of each switch has a maximum clamp voltage equal to VREF. A filter capacitor on VBIAS is recommended.