SCES625A February   2005  – November 2015 SN74VMEH22501A-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Live-Insertion Specifications
    7. 7.7  Timing Requirements for UBT Transceiver (I Version)
    8. 7.8  Switching Characteristics for Bus Transceiver Function (I Version)
    9. 7.9  Switching Characteristics for Bus Transceiver Function (M Version)
    10. 7.10 Switching Characteristics for UBT Transceiver (I Version)
    11. 7.11 Switching Characteristics for UBT Transceiver (M Version)
    12. 7.12 Switching Characteristics for Bus Transceiver Function (I Version)
    13. 7.13 Switching Characteristics for UBT (I Version)
    14. 7.14 Switching Characteristics for Bus Transceiver Function (I Version)
    15. 7.15 Switching Characteristics for UBT (I Version)
    16. 7.16 Skew Characteristics for Bus Transceiver (I Version)
    17. 7.17 Skew Characteristics for Bus Transceiver (M Version)
    18. 7.18 Skew Characteristics for UBT (I Version)
    19. 7.19 Skew Characteristics for UBT (M Version)
    20. 7.20 Skew Characteristics for Bus Transceiver (I Version)
    21. 7.21 Skew Characteristics for UBT (I Version)
    22. 7.22 Skew Characteristics for Bus Transceiver (I Version)
    23. 7.23 Skew Characteristics for UBT (I Version)
    24. 7.24 Maximum Data Transfer Rates
    25. 7.25 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Distributed-Load Backplane Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Functional Description for Two 1-Bit Bus Transceivers
      2. 9.3.2 Functional Description for 8-Bit UBT Transceiver
      3. 9.3.3 VMEbus Summary
    4. 9.4 Device Functional Modes
      1. 9.4.1 Direction Control Model (1-Bit Transceiver)
      2. 9.4.2 Direction Control for 8 Bit UBT
      3. 9.4.3 Latch Storage and Clock Storage
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The SN74VMEH22501A-EP device is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The SN74VMEH22501A-EP device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers.

9.2 Functional Block Diagram

SN74VMEH22501A-EP ld_ces357.gif
Pin numbers shown are for the DGG and DGV packages.
Figure 9. Logic Diagram (Positive Logic)

9.3 Feature Description

9.3.1 Functional Description for Two 1-Bit Bus Transceivers

The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are disabled.

Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y outputs are disabled.

The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields A data to B bus and an input low yields B data to Y bus.

Table 1. 1-Bit Bus Transceiver Function Table

INPUTS OUTPUT MODE
OEAB OEBY
L H Z Isolation
H H A data to B bus True driver
L L B data to Y bus
H L A data to B bus, B data to Y bus True driver with feedback path

9.3.2 Functional Description for 8-Bit UBT Transceiver

The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance state.

Table 2. Function Table

INPUTS OUTPUT
OE DIR
H X Z
L H 3A data to 3B bus
L L 3B data to 3A bus

The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For 3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data is latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB.

The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.

Table 3. UBT Transceiver Function Table(1)

INPUTS OUTPUT
3B		 MODE
OE LE CLKAB 3A
H X X X Z Isolation
L L H X B0(2) Latched storage of 3A data
L L L X B0(3)
L H X L L True transparent
L H X H H
L L ↑ L L Clocked storage of 3A data
L L ↑ H H
(1) 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
(2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LE went low.
(3) Output level before the indicated steady-state input conditions were established.

The UBT transceiver can replace any of the functions as shown in Table 4.

Table 4. SN74VMEH22501A-EP UBT Transceiver Replacement Functions(1)

FUNCTION 8 BIT
Transceiver '245, '623, '645
Buffer/driver '241, '244, '541
Latched transceiver '543
Latch '373, '573
Registered transceiver '646, '652
Flip-flop '374, '574
(1) SN74VMEH22501A-EP UBT transceiver replaces all above functions

9.3.3 VMEbus Summary

In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The data-transfer protocols used to define the VMEbus came from the Motorola® VERSA bus architecture that owed its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when introduced, defined two basic data-transfer operations: single-cycle transfers consisting of an address and a data transfer, and a block transfer (BLT) consisting of an address and a sequence of data transfers. These transfers were asynchronous, using a master-slave handshake. The master puts address and data on the bus and waits for an acknowledgment. The selected slave either reads or writes data to or from the bus, then provides a data-acknowledge (DTACK*) signal. The VMEbus system data throughput was 40 MBps. Previous to the VMEbus, it was not uncommon for the backplane buses to require elaborate calculations to determine loading and drive current for interface design. This approach made designs difficult and caused compatibility problems among manufacturers. To make interface design easier and to ensure compatibility, the developers of the VMEbus architecture defined specific delays based on a 21-slot terminated backplane and mandated the use of certain high-current TTL drivers, receivers, and transceivers.

In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer (2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade Association (VITA) established a task group to specify a synchronous protocol to increase data-transfer rates to 320 MBps, or more. The unreleased specification, VITA 1.5 [double-edge source synchronous transfer (2eSST)], is based on the asynchronous 2eVME protocol. It does not wait for acknowledgment of the data by the receiver and requires incident-wave switching. Sustained data rates of 1 GBps, more than ten times faster than traditional VME64 backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320 star-configuration backplane. The VME320 backplane approximates a lumped load, allowing substantially higher-frequency operation over the VME64x distributed-load backplane. Traditional VME64 backplanes with no changes theoretically can sustain 320 MBps.

From BLT to 2eSST – A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director, VITA, provides additional information on VMEbus and can be obtained at www.vita.com.

9.4 Device Functional Modes

True Driver With Feedback Path Mode (1-Bit Transceiver)

When OEAB is high and OEABYis s low, the 1-bit transceiver will act as true driver with a feedback path through the Y port for control and diagnostic monitoring.

9.4.1 Direction Control Model (1-Bit Transceiver)

The two 1 bit transceiver can act as a true driver when OEBY and OEAB are tied together.

  1. Input high:data move from A port to B bus
  2. Input low: data move from B port to Y bus

9.4.2 Direction Control for 8 Bit UBT

The UBT data flow is controlled by DIR pin. DIR set as high, it will be 3A-3B data flow and if DIR set as low, it will be 3B-3A dataflow. When LE is high, the UBT is in transparent mode and all inputs will be translated to the output.

9.4.3 Latch Storage and Clock Storage

When LE is low and CLK at high or low level, data is latched. During latch state, the output level is per the previous state. When the CLK transitions from low to high, the latched data will be output.