SCES625A February   2005  – November 2015 SN74VMEH22501A-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Live-Insertion Specifications
    7. 7.7  Timing Requirements for UBT Transceiver (I Version)
    8. 7.8  Switching Characteristics for Bus Transceiver Function (I Version)
    9. 7.9  Switching Characteristics for Bus Transceiver Function (M Version)
    10. 7.10 Switching Characteristics for UBT Transceiver (I Version)
    11. 7.11 Switching Characteristics for UBT Transceiver (M Version)
    12. 7.12 Switching Characteristics for Bus Transceiver Function (I Version)
    13. 7.13 Switching Characteristics for UBT (I Version)
    14. 7.14 Switching Characteristics for Bus Transceiver Function (I Version)
    15. 7.15 Switching Characteristics for UBT (I Version)
    16. 7.16 Skew Characteristics for Bus Transceiver (I Version)
    17. 7.17 Skew Characteristics for Bus Transceiver (M Version)
    18. 7.18 Skew Characteristics for UBT (I Version)
    19. 7.19 Skew Characteristics for UBT (M Version)
    20. 7.20 Skew Characteristics for Bus Transceiver (I Version)
    21. 7.21 Skew Characteristics for UBT (I Version)
    22. 7.22 Skew Characteristics for Bus Transceiver (I Version)
    23. 7.23 Skew Characteristics for UBT (I Version)
    24. 7.24 Maximum Data Transfer Rates
    25. 7.25 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Distributed-Load Backplane Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Functional Description for Two 1-Bit Bus Transceivers
      2. 9.3.2 Functional Description for 8-Bit UBT Transceiver
      3. 9.3.3 VMEbus Summary
    4. 9.4 Device Functional Modes
      1. 9.4.1 Direction Control Model (1-Bit Transceiver)
      2. 9.4.2 Direction Control for 8 Bit UBT
      3. 9.4.3 Latch Storage and Clock Storage
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Related Links
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

8.1 Distributed-Load Backplane Switching Characteristics

The switching characteristics tables show the switching characteristics of the device into the lumped load shown in this section (see Figure 7 and Figure 8). All logic devices currently are tested into this type of load. However, the designer's backplane application probably is a distributed load. For this reason, this device has been designed for optimum performance in the VME64x backplane as shown in Figure 6.

SN74VMEH22501A-EP backplane_ces357.gif
  1. Unloaded backplane trace natural impedance (ZO) is 45 Ω. 45 Ω to 60 Ω is allowed, with 50 Ω being ideal.
  2. Card stub natural impedance (ZO) is 60 Ω.
Figure 6. VME64x Backplane

The following switching characteristics tables derived from TI-SPICE models show the switching characteristics of the device into the backplane under full and minimum loading conditions, to help the designer better understand the performance of the VME device in this typical backplane.

SN74VMEH22501A-EP pmi_a_ces357.gif
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 7. A Port Load Circuit and Voltage Waveforms
SN74VMEH22501A-EP pmi_b_ces357.gif
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 8. B Port Load Circuit and Voltage Waveforms