SLLS131D September   1991  – October 2023 SN75ALS175

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Dissipation Rating Table
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Resistance Characteristics
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Device Functional Modes
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NS|16
  • N|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN75ALS175 is a monolithic quadruple differential line receiver with 3-state outputs. It is designed to meet the requirements of ANSI Standards EIA/TIA-422-B, EIA/TIA-423-B, and RS-485 and several ITU recommendations. Advanced low-power Schottky technology provides high speed without the usual power penalty. Each of the two pairs of receivers has a common active-high enable. The device features high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ±200 mV over a common-mode input voltage range of –12 V to 12 V.

The SN75ALS175 is characterized for operation from 0°C to 70°C.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
SN75ALS175 N (PDIP, 16) 19.3 mm × 9.4 mm
NS (SOP, 16) 10.2 mm × 7.8 mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-CC01426B-7878-4C9F-8FD8-3BC0BC93346E-low.pngFigure 3-1 Logic Symbol(1)
GUID-37B137E0-0168-4806-A03C-593B573DE1E3-low.pngLogic Diagram (Positive Logic)
†. This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.