SLLS697B December   2005  – June 2021 SN65C3232E , SN75C3232E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Protection
    3. 6.3  ESD Protection, Driver
    4. 6.4  ESD Protection, Receiver
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Thermal Information, SN65C3232E
    7. 6.7  Thermal Information, SN75C3232E
    8. 6.8  Electrical Characteristics, Power
    9. 6.9  Electrical Characteristics, Driver
    10. 6.10 Electrical Characteristics, Receiver
    11. 6.11 Switching Characteristics, Driver
    12. 6.12 Switching Characteristics, Receiver
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Functional Block Diagram
      2. 8.1.2 Feature Description
        1. 8.1.2.1 Power
        2. 8.1.2.2 RS232 Driver
        3. 8.1.2.3 RS232 Receiver
      3. 8.1.3 Device Functional Modes
        1. 8.1.3.1 VCC Powered by 3 V to 5.5 V
        2. 8.1.3.2 VCC Unpowered, VCC = 0 V
  9. 9 Application and Implenentation
    1. 9.1 Application Information
    2.     Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.12 Switching Characteristics, Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETERTEST CONDITIONS(3)TYP(1)UNIT
tPLHPropagation delay time, low- to high-level outputCL = 150 pF300ns
tPHLPropagation delay time, high- to low-level output300ns
tsk(p)Pulse skew(2)300ns
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.
(3) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V (see Figure 9-1).