SLLSE12A
November 2009 – July 2014
SN75DP119
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
Handling Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Pre-Emphasis and VOD Output Swing Setings
9.4
Device Functional Modes
9.4.1
Status Detect and Operating Modes Flow Diagram
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
11
Power Supply Recommendations
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
Device and Documentation Support
13.1
Trademarks
13.2
Electrostatic Discharge Caution
13.3
Glossary
14
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGY|14
MPQF114G
RHH|36
MPQF144E
Thermal pad, mechanical data (Package|Pins)
RGY|14
QFND039P
RHH|36
QFND054L
Orderable Information
sllse12a_oa
sllse12a_pm
12 Layout
12.1 Layout Guidelines
Data rates of 2.7Gbps require fast edge rate, which can cause EMI radiation if the pcb is not designed carefully.
Decoupling with small current loops is recommended.
It is recommended to place the de-coupling cap as close as possible to the device and on the same side of the pcb (see
Figure 12
).
Choose the capacitor such that the resonant frequency of the capacitor does not align closely with 2.7GHz.
Also provide several GND vias to the thermal pad to minimize the area of current loops.
12.2 Layout Example
Figure 12. De-Coupling Layout Recommendation