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  • SN75DP130 DisplayPort™ 1:1 Redriver With Link Training

    • SLLSE57E April   2011  – March 2015 SN75DP130

      PRODUCTION DATA.  

  • CONTENTS
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  • SN75DP130 DisplayPort™ 1:1 Redriver With Link Training
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Dissipation
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reset Signal
      2. 9.3.2 Hot Plug Detect and Cable Adapter Detect
      3. 9.3.3 AUX and DDC Configuration
      4. 9.3.4 Main Link Configuration
      5. 9.3.5 Link Training and DPCD
      6. 9.3.6 Equalization
      7. 9.3.7 Configurable Outputs
      8. 9.3.8 Squelch
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 I2C Interface Overview
    6. 9.6 Register Maps
      1. 9.6.1 SN75DP130 Local I2C Control and Status Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Logic I2C Interface
        2. 10.2.2.2 CAD Sink Over Ride
        3. 10.2.2.3 HPD Sink Over Ride
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 SN75DP130 Power Sequencing
      1. 11.1.1 Power-Up Sequence:
      2. 11.1.2 Power-Down Sequence:
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Differential Traces
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
  15. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RGZ|48
    • MPQF123F
Thermal pad, mechanical data (Package|Pins)
  • RGZ|48
    • QFND014T
Orderable Information
  • sllse57e_oa
  • sllse57e_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
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DATA SHEET

SN75DP130 DisplayPort™ 1:1 Redriver With Link Training

1 Features

  • Supports DP v1.1a and DP v1.2 Signaling Including HBR2 Data Rates to 5.4 Gbps
  • Supports HDMI 1.4b With TMDS Clock Frequencies up to 340 MHz
  • Glueless Interface to AMD, Intel, and NVIDIA Graphics Processors
  • Auto-Configuration Through Link Training
  • Output Signal Conditioning With Tunable Voltage Swing and Pre-Emphasis Gain
  • Highly Configurable Input Variable Equalizer
  • Two Device Options Including a Dual Power Supply Configuration for Lowest Power
  • 2-kV ESD HBM Protection
  • Temperature Range: 0°C to 85°C
  • 48-Pin 7-mm × 7-mm VQFN Package

2 Applications

  • Notebook PCs
  • Desktop PCs
  • PC Docking Stations
  • PC Standalone Video Cards

3 Description

The SN75DP130 device is a single channel DisplayPort™ (DP) re-driver that regenerates the DP high-speed digital link. The device complies with the VESA DisplayPort Standard Version 1.2, and supports a 4-lane Main Link interface signaling up to HBR2 rates at 5.4 Gbps per lane. This device also supports DP++ Dual-Mode, offering TMDS signaling for DVI and full HDMI Version 1.4a support.

The device compensates for PCB-related frequency loss and switching-related loss to provide the optimum DP electrical performance from source to sink. The Main Link signal inputs feature configurable equalizers with selectable boost settings. At the Main Link output, four primary levels of differential output voltage swing (VOD) and four primary levels of pre-emphasis are available. A secondary level of boost adjustment, programmed through I2C, for fine-tuning the Main Link output. The device can monitor the AUX channel and automatically adjust the output signaling levels and input equalizers in response to Link Training commands. Additionally, the SN75DP130 output signal conditioning and EQ parameters are fully programmable through the I2C interface.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN75DP130 VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simple Application

SN75DP130 app_photo_FP_llse57.gif

4 Revision History

Changes from D Revision (July 2013) to E Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from C Revision (January 2013) to D Revision

  • Power-Down Sequence deleted: 1. De-assert EN to the deviceGo
  • Power-Up Sequence deleted: 1. Assert RSTN and de-assert EN to the device.Go
  • Power-Up Sequence deleted: 5. Assert EN a minimum of 10 µs after RSTN has been de-asserted. Go
  • Deleted the EN time line from Figure 34Go

Changes from B Revision (October 2011) to C Revision

  • Added text to RSTN description in PIN FUNCTIONSGo
  • Added RSTN pin row to VIH in RECOMMENDED OPERATING CONDITIONSGo
  • Added RSTN pin row to VIL in RECOMMENDED OPERATING CONDITIONSGo
  • Added rows to Device power under normal operation in POWER DISSIPATION tableGo
  • Changed in Table 1 13.9 to 113.9Go
  • Deleted unnecessary tie dot in Block DiagramGo
  • Changed Table 3Go
  • Changed Figure 17Go
  • Changed Figure 18Go
  • Changed SN75DP130 Local I2C Control and Status RegistersGo
  • Added DP130 POWER SEQUENCING sectionGo

Changes from A Revision (September 2011) to B Revision

  • Deleted pins 37 an 43 from GND in the PIN FUNCTIONS tableGo

Changes from * Revision (April 2011) to A Revision

  • Changed pin numbers in PIN FUNCTIONS table, VDDD_DREG and NCGo

5 Description (continued)

The SN75DP130 is optimized for mobile applications, and contains activity detection circuitry on the Main Link input that transitions to a low-power Output Disable mode in the absence of a valid input signal. Other low-power modes are supported, including a standby mode with typical dissipation of approximately 2 mW when no video sink (for example, monitor) is connected.

The device is characterized for an extended operational temperature range from 0°C to 85°C.

The SN75DP130 offers separate AUX and DDC source interfaces that connect to one AUX sink channel. This minimizes component count when implemented with a graphics processor (GPU) comprising separate DDC and AUX interfaces. For GPUs with combined DDC/AUX, the device can operate as a FET switch to short-circuit the AUX channel AC coupling caps while connected to a TMDS sink device. Other sideband circuits such as Hot Plug Detect (HPD) are optimized to reduce external components, providing a seamless connection to Intel, AMD, and NVIDIA graphics processors.

6 Pin Configuration and Functions

SN75DP130SS RGZ Package
48-Pin VQFN Single Supply
Top View
SN75DP130 po1_llse57.gif
SN75DP130DS RGZ Package
48-Pin VQFN Dual Supply
Top View
SN75DP130 po2_llse57.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
MAIN LINK TERMINALS
IN0n 39 Input
(100-Ω diff)		 DisplayPort Main Link Lane 0 Differential Input
IN0p 38
IN1n 42 DisplayPort Main Link Lane 1 Differential Input
IN1p 41
IN2n 45 DisplayPort Main Link Lane 2 Differential Input
IN2p 44
IN3n 48 DisplayPort Main Link Lane 3 Differential Input
IN3p 47
OUT0n 22 Output
(100-Ω diff)		 DisplayPort Main Link Lane 0 Differential Output
OUT0p 23
OUT1n 19 DisplayPort Main Link Lane 1 Differential Output
OUT1p 20
OUT2n 16 DisplayPort Main Link Lane 2 Differential Output
OUT2p 17
OUT3n 13 DisplayPort Main Link Lane 3 Differential Output
OUT3p 14
AUX CHANNEL AND DDC DATA TERMINALS
AUX_SRCn 29 I/O
(100-Ω diff)		 Source Side Bidirectional DisplayPort Auxiliary Data Channel. If the AUX_SNK channel is used for monitoring only, these signals are not used and may be left open.
AUX_SRCp 30
AUX_SNKn 27 I/O
(100-Ω diff)		 Sink Side Bidirectional DisplayPort Auxiliary Data Channel.
AUX_SNKp 28
SDA_DDC 34 I/O Bidirectional I2C Display Data Channel (DDC) for TMDS mode. These signals may be used together with AUX_SNK to form a FET switch to short-circuit the AC coupling capacitors during TMDS operation in a DP++ Dual-Mode configuration. These terminals include integrated 60-kΩ pullup resistors
SCL_DDC 33
HPD, CAD, AND CONTROL TERMINALS
HPD_SRC 9 O Hot Plug Detect Output to the DisplayPort Source.
HPD_SNK 11 I DisplayPort Hot Plug Detect Input from Sink. This device input is 5-V tolerant.
Note: Pull this input high during compliance testing or use I2C control interface to go into compliance test mode and control HPD_SNK and HPD_SRC by software.
CAD_SRC 8 O DP Cable Adapter Detect Output. This output typically drives the GPU CAD input.
CAD_SNK 10 I DisplayPort Cable Adapter Detect Input. This input tolerates a 5-V supply with a supply impedance higher than 90kΩ. A device internal zener diode limits the input voltage to 3.3 V.
An external 1MΩ resistor to GND is recommended. This terminal is used to select DP mode or TMDS mode in a DP++ Dual-Mode application.
SCL_CTL 4 I/O Bidirectional I2C interface to configure the SN75DP130. This interface is active independent of the EN input but inactive when RSTN is low.
SDA_CTL 5
RSTN 35 I Active Low Device Reset. This input includes a 150-kΩ resistor to the VDDD core supply. An external capacitor to GND is recommended on the RSTN input to provide a power-up delay (see the VIL and VIH specifications in Recommended Operating Conditions).
This signal is used to place the SN75DP130 into Shutdown mode for the lowest power consumption. When the RSTN input is asserted, all outputs (excluding HPD_SRC and CAD_SRC) are high-impedance, and inputs (excluding HPD_SNK and CAD_SNK) are ignored; all I2C and DPCD registers are reset to their default values.
At power up, the RSTN input must not be de-asserted until the VCC and VDDD supplies have reached at least the minimum recommended supply voltage level (see Figure 34 for timing requirements).
EN 26 I Device Enable. This input incorporates an internal pullup of 200 kΩ.
ADDR_EQ 3 3-level Input I2C Target Address Select and EQ Configuration Input. If the I2C bus is used, this input setting selects the I2C target address, as described in Figure 19. This input also configures the input EQ to the device, as described in Table 3.
SUPPLY AND GROUND TERMINALS
VDDD SN75DP130DS
6, 12, 15, 21, 25, 32, 37, 43		 Digital low voltage core and Main Link supply for SN75DP130DS device option.
Nominally 1.1 V.
VCC SN75DP130SS
1, 6, 12, 25, 32, 36		 3.3-V Supply
SN75DP130DS
1, 36
VDDD_DREG 2 SN75DP130SS: Digital voltage regulator decoupling; install 1 µF to GND.
SN75DP130DS: Treat same as VDDD; this pin will be most noisy of all VDDD terminals and needs a decoupling capacitor nearby.
GND 18, 24, 31, and
Exposed Thermal Pad		 Ground. Reference GND connections include the device package exposed thermal pad.
NC SN75DP130SS
7, 15, 21, 37, 40, 43, 46		 No Connect. These terminals may be left unconnected, or connect to GND.
SN75DP130DS
7, 40, 46

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VCC –0.3 4 V
VDDD, VDDD_DREG –0.3 1.3
Voltage Main link I/O differential voltage –0.3 1.3 V
HPD_SNK –0.3 5.5
All other terminals –0.3 4
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VDDD Digital core and Main Link supply voltage 0.97 1.05 1.2 V
TA Operating free-air temperature 0 85 °C
TCASE Case temperature 103.1 °C
VIH(HPD) High-level input voltage HPD_SNK 1.9 5.5 V
VIH High-level input voltage for device control signals 1.9 3.6 V
RSTN pin (typical hysteresis of 80 mV) 0.75
VIL Low-level input voltage for device control signals 0 0.8 V
RSTN pin (typical hysteresis of 80 mV) 0.3
MAIN LINK TERMINALS
VID Peak-to-peak input differential voltage; RBR, HBR, HBR2 0.3 1.40 Vpp
dR Data rate 5.4 Gbps
CAC AC coupling capacitance (each input and each output line) 75 200 nF
Rtdiff Differential output termination resistance 80 100 120 Ω
VOterm Output termination voltage (AC coupled) 0 2 V
tSK(in HBR2) Intra-pair skew at the input at 5.4 Gbps When used as re-driver in DP source 20 ps
When used as receiver equalizer in DP sink 100
tSK(in HBR) Intra-pair skew at the input at 2.7 Gbps 100 ps
tSK(in RBR) Intra-pair skew at the input at 1.62 Gbps 300 ps
AUX CHANNEL DATA TERMINALS
VI-DC DC input voltage AUX_SRCp and AUX_SNKp in DP mode –0.5 0.3 0.4 V
AUX_SRCn and AUX_SNKn in DP mode 2 3 3.6
AUX_SRCp/n and AUX_SNKp/n in TMDS mode –0.5 3.6
VID Differential input voltage amplitude (DP mode only) 300 1400 mVPP
dR(AUX) Data rate (before Manchester encoding) 0.8 1 1.2 Mbps
dR(FAUX) Data rate Fast AUX (300ppm frequency tolerance) 720 Mbps
tjccin_adj Cycle-to-cycle AUX input jitter adjacent cycle (DP mode only) 0.05 UI
tjccin Cycle-to-cycle AUX input jitter within one cycle (DP mode only) 0.1 UI
CAC AUX AC coupling capacitance (DP mode only) 75 200 nF
VsrcCMM AUX source common mode voltage (only applies to DP mode)
CAD = VIL; measured on AUX source and sink before AC coupling caps		 0 2000 mV
DDC AND I2C TERMINALS
VI Input voltage –0.5 3.6 V
dR Data rate 100 kbps
VIH High-level input voltage 0.7 VCC V
VIL Low-level input voltage 0.3 VCC V
fSCL SCL clock frequency standard I2C mode 100 kHz
tw(L) SCL clock low period standard I2C mode 4.7 µs
tw(H) SCL clock high period standard I2C mode 4 µs
Cbus Total capacitive load for each bus line 400 pF

7.4 Thermal Information

THERMAL METRIC(1) SN75DP130 UNIT
RGZ (VQFN)
48 PINS
RθJA Junction-to-ambient thermal resistance 35.1 °C/W
RθJCtop Junction-to-case (top) thermal resistance 21.5
RθJB Junction-to-board thermal resistance 11.7
ψJT Junction-to-top characterization parameter, high-k board 1.2
ψJB Junction-to-board characterization parameter, high-k board 11.9
RθJCbot Junction-to-case (bottom) thermal resistance 6.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Power Dissipation

See SN75DP130 Power Sequencing.
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
PN Device power under normal operation SN75DP130SS; 4 DP Lanes. 468 828 mW
SN75DP130DS; 4 DP Lanes. 174 304
SN75DP130SS; 2 DP Lanes 252 450
SN75DP130DS; 2 DP Lanes. 102 178
SN75DP130SS; 1 DP Lanes 144 252
SN75DP130DS; 1 DP Lanes. 66 112
PSD Shutdown mode power dissipation SN75DP130SS; 4 DP Lanes. 14.4 mW
SN75DP130DS; 4 DP Lanes. 7.2
PSBY Standby mode power dissipation SN75DP130SS; 4 DP Lanes. 14.4 mW
SN75DP130DS; 4 DP Lanes. 7.2
PD3 D3 power down mode dissipation SN75DP130SS; 4 DP Lanes. 54 mW
SN75DP130DS; 4 DP Lanes. 46
POD Output disable (squelch) mode current SN75DP130SS; 4 DP Lanes. 126 180 mW
SN75DP130DS; 4 DP Lanes. 58 88
(1) Test conditions correspond to Power Supply test conditions in Electrical Characteristics

7.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICCDP1HBR2 Supply Current 1 DP Lanes Maximum conditions: IN/OUT at 5.4 Gbps
PRBS,VOD = 510 mVpp, PE = 6 dB; AUX at 1 Mbps
PRBS, VID = 1000 mVpp; EQ = 3.5 dB
Typical Conditions: IN/OUT at 5.4 Gbps
PRBS,VOD = 510 mVpp, PE = 0dB AUX and I2C
Idle; EQ = 5 3dB		 40 70 mA
ICCDP2HBR2 Supply Current 2 DP Lanes 70 125 mA
ICCDP4HBR2 Supply Current 4 DP Lanes 130 230 mA
ICCDP1HBR Supply Current 1 DP Lanes Main Link at 2.7Gbps PRBS, VOD = 510 mVpp,
PE = 0 dB; AUX and I2C Idle; EQ at 3 dB fixed gain		 40 mA
ICCDP2HBR Supply Current 2 DP Lanes 70 mA
ICCDP4HBR Supply Current 4 DP Lanes 130 mA
ICCTMDS Supply Current TMDS Mode Main Link at 2.5 Gbps PRBS, VID = VOD = 600 mVpp;
AUX Idle		 170 mA
ISD Shutdown supply current Shutdown mode 3 4 mA
ISBY Standby supply current Standby mode 3 4 mA
ID3 D3 supply current D3 power-down mode 10 15 mA
IOD Squelch supply current Output disable (Squelch) mode 35 50 mA
MAIN LINK
VOD(L0) Output differential voltage swing VPRE(L0); 675 Mbps D10.2 Test Pattern; BOOST = 01 238 340 442 mVPP
VOD(L1) 357 510 663
VOD(L2) 484 690 897
VOD(L3) 700 1000 1300
VOD(TMDS) 675 Mbps D10.2 Test Pattern; BOOST = 01 420 600 780
ΔVOD(L0L1) Output peak-to-peak differential voltage delta ΔVODn = 20×log(VODL(n+1) / VODL(n)) measured in compliance with PHY CTS1.1D15 section 3.2 at test point TP2 using special CTS test board 1.7 3.5 5.3 dB
ΔVOD(L1L2) 1.6 2.5 3.5
ΔVOD(L2L3) 0.8 3.5 6
VPRE(L0) Driver output pre-emphasis (default) All VOD options 0 0.25 dB
VPRE(L1) VOD = VOD(L0), VOD(L1), or VOD(L2); BOOST = 01 3.5
VPRE(L2) VOD = VOD(L0) or VOD(L1); BOOST = 01 6
VPRE(L3) VOD = VOD(L0); BOOST = 01 9.5
VPRE(BOOST) Output VPRE boost BOOST = 10 10% dB
BOOST = 00 –10%
ΔVPRE(L1L0) Pre-emphasis delta Measured in compliance with PHY CTS1.1D15 section 3.3 at test point TP2 using special CTS test board 2 dB
ΔVPRE(L2L1) 1.6
ΔVPRE(L3L2) 1.6
ΔVConsBit Nontransition bit voltage variation See CTS spec section 3.3.5 30%
AEQ(HBR) Equalizer gain for RBR/HBR See Table 3 for EQ setting details;
Max value represents the typical value for the maximum configurable EQ setting		 9 dB
AEQ(HBR2) Equalizer gain for HBR2 18 dB
AEQ(TMDS) Equalizer gain for TMDS 3 dB
ROUT Driver output impedance 50 Ω
RIN Input termination impedance 40 50 60 Ω
VIterm Input termination voltage AC coupled; self-biased 0 2 V
VOCM(SS) Steady state output common-mode voltage 0 2 V
ΔVOCM(SS) Change in steady state output common-mode voltage between logic levels Tested in compliance to section 3.10 in CTS 1.1a 10 mVPP
VOCM(PP) Output common-mode noise HBR2 20 mVRMS
30
VSQUELCH Squelch threshold voltage Programable through I2C; default at 80 mVpp typical 80 mVPP
ITXSHORT Short circuit current limit Main Link outputs shorted to GND 50 mA
HPD_SRC, CAD_SRC
VOH High-level output voltage IOH = 500 µA 2.7 3.6 V
VOL Low-level output voltage IOH = 500 µA 0 0.1 V
RoutCAD CAD series output resistance(2) EN = RSTN = VCC; HPD_SNK = CAD_SNK = VCC 150 Ω
RoutHPD HPD series output resistance EN = RSTN = VCC; HPD_SNK = CAD_SNK = VCC 150 Ω
ILEAK Leakage current (3) VCC = 0 V, V(pin) = 1.2 V; RSTN 20 μA
VCC = 0 V, V(pin) = 3.3 V; SCL/SDA_CTL, AUX_SNKp/n 20
VCC = 0 V, V(pin) = 3.3 V; HPD_SNK 40
VCC = 0 V, V(pin) = 3.3 V; AUX_SRCp/n 60
HPD_SNK
IH High-level input current VIH = 1.9 V (leakage includes the 130-kΩ pull-down resistor) –30 30 µA
IL Low-level input current VIL = 0.8 V (leakage includes the 130-kΩ pull-down resistor) –30 30 µA
VTH+ Positive going input threshold voltage 1.4 V
RpdHPD HPD input termination to GND VCC = 0 V 100 130 160 kΩ
CAD_SNK
IH High-level input current VIH = 1.9 V –1 1 µA
IL Low-level input current VIL = 0.8 V –1 1 µA
VTH+ Positive going input threshold voltage 1.4 V
AUX/DDC/I2C
VPASS DDC mode passthrough voltage VCAD_SNK = VIH; IO = 100 µA 1.9 V
CIO I/O capacitance VIO = 0 V; f(test) = 1 MHz 10 pF
rON On resistance AUX_SRCn to AUX_SNKn in DP mode VCC = 3 V w/ VI = 2.85 V or
VCC = 3.6 V w/ VI = 3.4 V; IO = 5 mA		 5 10 Ω
On resistance SCL/SDA_DDC to AUX_SNK in TMDS mode IO = 3 mA 15 30
On resistance AUX_SRC to AUX_SNK in TMDS mode IO = 3 mA 10 20
ΔrON On resistance variation with input signal voltage change in DP mode VCC = 3.6 V, IO = 5 mA, VI = 2.6 to 3.4 V,
VCC = 3 V, IO = 5 mA, VI = 0 to 0.4 V		 5 Ω
VID(HYS) Differential input hysterisis By design (simulation only) 50 mV
IH High-level input current VI = VCC –5 5 µA
IL Low-level input current VI = GND; CAD_SNK = VIH –5 5 µA
VI = GND; At DDC inputs 80
VAUX+ Voltage on the Aux+ for PHY-CTS 3.19 1M (5%) pullup to VCC and 100-kΩ pulldown to GND on AUX+; VCC = 3.3 V 0 0.4 V
VAUX- Voltage on the Aux- for PHY-CTS 3.18 100 kΩ pullup to VCC and 1M (5%) pulldown to GND on AUX-;
VCC = 3.3 V		 2.4 3.6 V
|S1122| Differential line insertion loss VID = 400 mV, AC coupled; p-channel biasing 0.3 V and
N-channel 3 V; 360-MHz sine wave; CAD_SNK = VIL 		1.6 3 dB
RDDC Switcheable pul-lup resistor on DDC at source side (SCL_DDC, SDA_DDC) CAD_SNK = VIH 48 60 72 kΩ
(1) Values are VDD supply measurements; VCC supply (DS package option) measurements are 5 mA (typical) and 8 mA (max), with zero current in shutdown and standby modes.
(2) A series output resistance of 100kΩ may be added in series to the CAD_SRC output to mimic a cable adapter.
(3) Applies to failsafe inputs: RSTN, SDA_CTL, SCL_CTL, SDA_DDC, SCL_DDC, AUX_SNK P/N, AUX_SRC P/N, HPD_SNK

7.7 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MAIN LINK
tPD Propagation delay time See Figure 10 300 ps
tSK(1) Intra-pair output skew Signal input skew = 0ps; dR = 2.7 Gbps, VPRE = 0 dB, 800 mVp-p, D10.2 clock pattern at device input; See Figure 11 20 ps
tSK(2) Inter-pair output skew 100 ps
Δtjit Total peak-to-peak residual jitter VOD(L0); VPRE(L0); EQ = 8 dB; clean source; minimum input and output cabling; 1.62 Gbps, 2.7 Gbps, and 5.4 Gbps PRBS7 data pattern. 15 ps
tsq_enter Squelch entry time Time from active DP signal turned off to ML output off with noise floor minimized 10 120 μs
tsq_exit Squelch exit time Time from DP signal on to ML output on 0 1 μs
HPD/CAD
tPD(HPD) Propagation delay HPD_SNK to HPD_SRC VCC = 3 V; See Figure 1 50 ns
tPD(CAD) Propagation delay CAD_SNK to CAD_SRC 50 ns
tT(HPD) HPD logic shut off time VCC = 3 V; See Figure 2 400 ms
AUX/DDC/I2C
tsk(AUX) Intra-pair skew VID = 400 mV, AC coupled; p-channel biasing 0.3V and
N-channel 3 V; See Figure 13		 400 ps
tPLH(DP) Propagation delay time, low to high CAD = VIL; 1-Mbps pattern;See Figure 14 3 ns
tPHL(DP) Propagation delay time, high to low 3 ns
tPLH(DDC) Propagation delay time, low to high CAD = VIH; 100-kbps pattern 50 ns
tPHL(DDC) Propagation delay time, high to low 50 ns
tPU(AUX) Main Link D3 wake-up time VID = 0.1 V, VICMM = 2-V source side (before AC coupling caps) 50 µs
I2C
Refer to the I2C-Bus Specification, Version 2.1 (January 2000); SN75DP130 meets the switching characteristics for standard mode transfers up to 100 kbps.

SN75DP130 timing1_llse57.gifFigure 1. HPD Timing Diagram 1
SN75DP130 timing2_llse57.gifFigure 2. HPD Timing Diagram 2

7.8 Typical Characteristics

Table 1. Characterization Test Board Trace Lengths Related to Input Jitter

INPUT MODE TRACE LENGTH (INCHES) TOTAL INPUT JITTER (ps) RECOMMENDED EQ SETTING
Display Port HBR2 2 14.4 8
6 23.1 8
10 38.8 10
14 58.9 10
18 84.8 13
22 113.9 13
TMDS 3.4 Gbps 2 15.8 6
6 21.3 6
10 33.2 6
14 49.9 13
18 70.5 13
22 91.5 13
SN75DP130 G1_llse57.gif
Gain represents SN75DP130 design simulation.
Figure 3. Typical EQ Gain Curves
SN75DP130 G2_llse57.gif
DisplayPort output jitter measured at the surface mount pins connected to the main link output channels on the SN75DP130 characterization test board; input jitter generated from test board with variable input trace lengths using 4 mil traces of lengths 2 inches to 22 inches generating the typical input jitter as represented in Table 1.
Figure 4. DisplayPort Sink Jitter Performance With Optimal EQ Settings
SN75DP130 G4_llse57.gif
DisplayPort output jitter measured at the surface mount pins connected to the main link output channels on the SN75DP130 characterization test board; input jitter generated from test board with variable input trace lengths using 4 mil traces of lengths 2 inches to 22 inches generating the typical input jitter as represented in Table 1.
Figure 5. TMDS Sink jitter Performance With Optimal EQ Settings
SN75DP130 G6_llse57.gifFigure 7. SN75DP130 Output; 10-Inch Input Trace; 13-dB EQ Setting; DP Sink
SN75DP130 G8_llse57.gifFigure 9. SN75DP130 Output; 10-Inch Input Trace; 13-dB EQ Setting; TMDS Sink
SN75DP130 G5_llse57.gif
Figure 6. Main Link Input With 10-Inch Trace; DisplayPort Sink
SN75DP130 G7_llse57.gifFigure 8. Main Link Input With 10-Inch Trace; TMDS Sink

 
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