SLLSEL2C September   2015  – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 HPD Switching Characteristics
    12. 7.12 DDC and I2C Switching Characteristics
    13. 7.13 Parameter Measurement Information
    14. 7.14 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reset Implementation
      2. 8.3.2 Operation Timing
      3. 8.3.3 Input Lane Swap and Polarity Working
      4. 8.3.4 Main Link Inputs
      5. 8.3.5 Main Link Inputs Debug Tools
      6. 8.3.6 Receiver Equalizer
      7. 8.3.7 Termination Impedance Control
      8. 8.3.8 TMDS Outputs
        1. 8.3.8.1 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 DP-HDMI Adaptor ID Buffer
      2. 8.5.2 Local I2C Interface Overview
      3. 8.5.3 I2C Control Behavior
      4. 8.5.4 I2C Control and Status Registers
        1. 8.5.4.1 Bit Access Tag Conventions
        2. 8.5.4.2 CSR Bit Field Definitions
          1. 8.5.4.2.1 ID Registers
          2. 8.5.4.2.2 Misc Control
          3. 8.5.4.2.3 HDMI Control
          4. 8.5.4.2.4 Equalization Control Register
          5. 8.5.4.2.5 EyeScan Control Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Use Case of SNx5DP149
      2. 9.1.2 DDC Pullup Resistors
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Compliance Testing
  10. 10Power Supply Recommendations
    1. 10.1 Power Management
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RSB Package
40-Pin WQFN
Top View
SN65DP149 SN75DP149 po_RSB_SLLSEJ2.gif

Pin Functions

PIN I/O DESCRIPTION (1)
SIGNAL NAME NO.
MAIN LINK INPUT PINS (FAIL SAFE)
IN_D2p
IN_D2n 		1
2 		I Channel 2 differential input
IN_D1p
IN_D1n		 4
5		 I Channel 1 differential input
IN_D0p
IN_D0n		 6
7		 I Channel 0 differential input
IN_CLKp
IN_CLKn		 9
10		 I Clock differential input
MAIN LINK OUTPUT PINS (FAIL SAFE)
OUT_D2n
OUT_D2p		 29
30		 O TMDS data 2 differential output
OUT_D1n
OUT_D1p		 26
27		 O TMDS data 1 differential output
OUT_D0n
OUT_D0p		 24
25		 O TMDS data 0 differential output
OUT_CLKn
OUT_CLKp		 21
22		 O TMDS data clock differential output
HOT PLUG DETECT PINS
HPD_SRC 3 O Hot plug detect output
HPD_SNK 28 I (Failsafe) Hot plug detect input
DDC DATA PINS
SDA_SRC
SCL_SRC		 39
38		 I/O (Failsafe) Source side TMDS port bidirectional DDC data line
SDA_SNK
SCL_SNK		 33
32		 I/O (Failsafe) Sink side TMDS port bidirectional DDC data lines
CONTROL PINS
OE 36 I Operation enable/reset pin
OE = L: Power-down mode
OE = H: Normal operation
Internal weak pullup: Resets device when transitions from H to L
SLEW_CTL 34 I
3
level (1)		 Slew rate control when I2C_EN/PIN = Low. SLEW_CTL = H, fastest data rate (default)
SLEW_CTL = L, 5-ps slow
SLEW_CTL = No Connect, 10-ps slow
When I2C_EN/PIN = High Slew rate is controlled through I2C[4]
PRE_SEL 16 I
3
level (1)		 PRE_SEL = L: - 2-dB de-emphasis
PRE_SEL = No Connect: 0-dB
PRE_SEL = H: Reserved
Note: (3 level for pin strap programming, but 2 level when I2C[4] address)
EQ_SEL/A0 17 I
3
level (1)		 Input Receive Equalization pin strap when I2C_EN/PIN = Low
EQ_SEL = L: Fixed EQ at 7.5-dB
EQ_SEL = No Connect: Adaptive EQ
EQ_SEL = H: Fixed at 14-dB
When I2C_EN/PIN = High
Address bit 1
Note: (3 level for pin strap programming but 2 level when I2C[4] address)
I2C_EN/PIN 8 I I2C_EN/PIN = High; puts device into I2C control mode
I2C_EN/PIN = Low; puts device into pin strap mode
SCL_CTL 13 I I2C clock signal
Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be changed by I2C
SDA_CTL 14 I/0 I2C data signal
Note: When I2C_EN/PIN = Low Pin strapping take priority and those functions cannot be changed by I2C
Vsadj 18 I TMDS-compliant voltage swing control nominal resistor to GND
HDMI_SEL/A1 23 I HDMI_SEL when I2C_EN/PIN = Low
HDMI_SEL = High: Device configured for DVI
HDMI_SEL = Low: Device configured for HDMI (Adaptor ID block is readable through I2C
When I2C_EN/PIN = High
Address bit 2
Note: Weak internal pull down
SUPPLY AND GROUND PINS
VCC 11, 37 P 3.3-V power supply
VDD 12, 19, 20, 31, 40 P 1.1-V power supply
GND 15, 35, Thermal Pad — Ground
  1. (H) Logic high (pin strapped to VCC through 65-kΩ resistor); (L) logic low (pin strapped to GND through 65-kΩ resistor); (for mid-level, no connect)