SLLSEL2C September   2015  – July 2016 SN65DP149 , SN75DP149

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Supply Electrical Characteristics
    6. 7.6  Differential Input Electrical Characteristics
    7. 7.7  HDMI and DVI TMDS Output Electrical Characteristics
    8. 7.8  DDC, and I2C Electrical Characteristics
    9. 7.9  HPD Electrical Characteristics
    10. 7.10 HDMI and DVI Main Link Switching Characteristics
    11. 7.11 HPD Switching Characteristics
    12. 7.12 DDC and I2C Switching Characteristics
    13. 7.13 Parameter Measurement Information
    14. 7.14 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reset Implementation
      2. 8.3.2 Operation Timing
      3. 8.3.3 Input Lane Swap and Polarity Working
      4. 8.3.4 Main Link Inputs
      5. 8.3.5 Main Link Inputs Debug Tools
      6. 8.3.6 Receiver Equalizer
      7. 8.3.7 Termination Impedance Control
      8. 8.3.8 TMDS Outputs
        1. 8.3.8.1 Pre-Emphasis/De-Emphasis
    4. 8.4 Device Functional Modes
      1. 8.4.1 Retimer Mode
      2. 8.4.2 Redriver Mode
      3. 8.4.3 DDC Functional Description
    5. 8.5 Register Maps
      1. 8.5.1 DP-HDMI Adaptor ID Buffer
      2. 8.5.2 Local I2C Interface Overview
      3. 8.5.3 I2C Control Behavior
      4. 8.5.4 I2C Control and Status Registers
        1. 8.5.4.1 Bit Access Tag Conventions
        2. 8.5.4.2 CSR Bit Field Definitions
          1. 8.5.4.2.1 ID Registers
          2. 8.5.4.2.2 Misc Control
          3. 8.5.4.2.3 HDMI Control
          4. 8.5.4.2.4 Equalization Control Register
          5. 8.5.4.2.5 EyeScan Control Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Use Case of SNx5DP149
      2. 9.1.2 DDC Pullup Resistors
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 Compliance Testing
  10. 10Power Supply Recommendations
    1. 10.1 Power Management
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power Management

To minimize the power consumption of customer application, SNx5DP149 uses dual power supply. VCC is 3.3-V with 10% range to support the I/O voltage. The VDD is 1.00-V to 1.27-V range to supply the internal digital control circuit. SNx5DP149 operates in two different working states. See Table 14 for conditions for each mode. When OE is deasserted and then reasserted the device will rest to its default configurations. If different configurations were programmed using I2C then the device will have to be reprogrammed.

  • Power-down mode:
    • OE = Low puts the device into its lowest power state by shutting down all function blocks
      • When OE is re-asserted the transitions from L → H will create a reset and if the device is programmed through I2C it will have to be reprogrammed.
      • OE = High, HPD_SNK = Low
      • Writing a 1 to register 09h[3]
  • Normal operation: Working in redriver or retimer
  • When HPD asserts, the device CDR and output will enable based on the signal detector circuit result
  • HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when VCC over 3-V.

    Table 14. Control Logic and Mode of Operation

    INPUTS(1) STATUS MODE
    HPD_SNK OE Mode of Operation HPD_SRC IN_Dx SDA_CTL
    SCL_CTL    		 OUT_Dx
    OUT_CLK    		 DDC
    H L X H High-Z Disabled High-Z Disabled Power-down mode
    L H X L High-Z Active High-Z Disabled Power-down mode
    H H X H High-Z Active High-Z Disabled Power-down mode when a one is written to 09h[3]
    H H Redriver H RX active Active TX active Active Normal operation
    H H Retimer H RX active Active TX active Active Normal operation
    (1) L = LOW, H = HIGH

    TMDS output termination control impacts the operating power.