SLLSEO9D March   2016  – October 2024 SN65DPHY440SS , SN75DPHY440SS

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics, Power Supply
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 HS Receive Equalization
      2. 6.3.2 HS TX Edge Rate Control
      3. 6.3.3 TX Voltage Swing and Pre-Emphasis Control
      4. 6.3.4 Dynamic De-skew
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 LP Mode
      3. 6.4.3 ULPS Mode
      4. 6.4.4 HS Mode
    5. 6.5 Register Maps
      1. 6.5.1  BIT Access Tag Conventions
      2. 6.5.2  Standard CSR Registers (address = 0x000 - 0x07)
      3. 6.5.3  Standard CSR Register (address = 0x08)
      4. 6.5.4  Standard CSR Register (address = 0x09)
      5. 6.5.5  Standard CSR Register (address = 0x0A)
      6. 6.5.6  Standard CSR Register (address = 0x0B)
      7. 6.5.7  Standard CSR Register (address = 0x0D)
      8. 6.5.8  Standard CSR Register (address = 0x0E)
      9. 6.5.9  Standard CSR Register (address = 0x10) [reset = 0xFF]
      10. 6.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
  8. 7 Application and Implementation
    1. 7.1 Application Information,
    2. 7.2 Typical Application, CSI-2 Implementations
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Reset Implementation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision C (August 2019) to Revision D (October 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed all instances of legacy terminology to controller and target where I2C is mentionedGo
  • Changed tHD;DAT units from μs to ns in the Timing Requirements tableGo
  • Changed tSU;DAT from 4μs minimum to 250ns minimum in the Timing Requirements tableGo
  • Added fCLK parameter in the Timing Requirements tableGo

Changes from Revision B (August 2017) to Revision C (August 2019)

  • Changed F(BR) MAX value From: 1 Gbps To: 1.5 Gbps in the Switching Characteristics tableGo

Changes from Revision A (April 2016) to Revision B (August 2017)

  • Changed Feature From: CSI-2/DSI Clock Rates From 100 MHz to 500 MHz To: CSI-2/DSI Clock Rates From 100 MHz to 750 MHz Go
  • Changed text in the Description From: MIPI DSI application at datarates of up to 1 Gbps. To: MIPI DSI application at datarates of up to 1.5 Gbps.Go
  • Changed VIH = 4 dB To: VIH = 5 dB in the Pin Functions tableGo
  • Added a Test Condition of EQ is at 750 MHz to V(RXEQ1) n the Electrical Characteristics tableGo
  • Changed V(RXEQ2) TYP value From: 4 dB To: 5 dB in the Electrical Characteristics table Go
  • Changed the MIPI DPHY HS Interface section in the Timing Requirements tableGo
  • Changed F(HSCLK) From 500 µsMHz To: 750 MHz in the Switching Characteristics tableGo
  • Changed F(DESKEW) from 500 MHz To: 750 MHz. Go
  • Changed tR and tF Datarate Test Conditions and values Go
  • Changed text From: application at datarates of up to 1 Gbps To: application at datarates of up to 1.5 Gbps in the Overview sectionGo
  • Changed Table 6-1 Go
  • Changed 11 – 4 dB To: 11 – 5 dB for RXEQ_CLK in Table 6-8 Go
  • Changed 11 – 4 dB To: 11 – 5 dB for RXEQ_DATA in Table 6-8 Go
  • Changed From: Data Rate To: Data Rate (200 Mbps to 1.5 Gbps) in Table 7-1 Go

Changes from Revision * (March 2016) to Revision A (April 2016)

  • Changed Features From: 3-kV ESD HBM Protection To: 2-kV ESD HBM ProtectionGo
  • Changed From: (approx. 100K) To: (100K) in the Pin Functions table for pins 13 and 14Go
  • Changed From: (approx. 100K) To: (100K) in the Pin Functions table for pins 26, 27, and 28Go
  • Changed ESD Ratings values. HBM From: ±2000 To: ±3000, and CDM Form: ±500 To: ±1000 Go
  • Changed V(RXEQ2) TYP value From: 5 dB To: 4 dB in the Electrical Characteristics table Go
  • Added MIN and MAX values to |VOD(VD0)|, |VOD(VD1)|, and |VOD(VD2)| in the Electrical Characteristics tableGo
  • Deleted rows ZOS and ΔZOS from the Electrical Characteristics tableGo
  • Updated the MIPI DPHY LP Transmitter Interface section of the Switching Characteristics tableGo
  • Changed 5 dB to 4 dB in HS Receive Equalization and Table 6-1 Go
  • Changed 11 – 4 dB To: 11 – 5 dB in Table 6-8 Go