SLLS505P February   2002  – February 2022 SN65HVD10 , SN65HVD11 , SN65HVD12 , SN75HVD10 , SN75HVD11 , SN75HVD12

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Power Dissipation Characteristics
    8. 7.8  Driver Switching Characteristics
    9. 7.9  Receiver Switching Characteristics
    10. 7.10 Dissipation Ratings
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low-Power Standby Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Fail-safe
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
      1. 12.3.1 Thermal Characteristics of IC Packages
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Driver Switching Characteristics

Over recommended operating conditions unless otherwise noted
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
tPLHPropagation delay time, low-to-high-level outputHVD10RL = 54 Ω, CL = 50 pF
See Figure 8-4		58.516ns
HVD11182540
HVD12135200300
tPHLPropagation delay time, high-to-low-level outputHVD1058.516ns
HVD11182540
HVD12135200300
trDifferential output signal rise timeHVD1034.510ns
HVD11102030
HVD12100170300
tfDifferential output signal fall timeHVD1034.510ns
HVD11102030
HVD12100170300
tsk(p)Pulse skew (|tPHL – tPLH|)HVD101.5ns
HVD112.5
HVD127
tsk(pp)(2)Part-to-part skewHVD106ns
HVD1111
HVD12100
tPZHPropagation delay time, high-impedance-to-high-level outputHVD10RL = 110 Ω, RE at 0 V
See Figure 8-5		31ns
HVD1155
HVD12300
tPHZPropagation delay time, high-level-to-high-impedance outputHVD1025ns
HVD1155
HVD12300
tPZLPropagation delay time, high-impedance-to-low-level outputHVD10RL = 110 Ω, RE at 0 V
See Figure 8-6		26ns
HVD1155
HVD12300
tPLZPropagation delay time, low-level-to-high-impedance outputHVD1026ns
HVD1175
HVD12400
tPZHPropagation delay time, standby-to-high-level outputRL = 110 Ω, RE at 3 V
See Figure 8-5		6μs
tPZLPropagation delay time, standby-to-low-level outputRL = 110 Ω, RE at 3 V
See Figure 8-6		6μs
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.