SLLSE63A December   2010  – May 2016 SN75LVCP600

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Equalization
      2. 9.3.2 Auto Low Power (ALP) Mode
      3. 9.3.3 Out-of-Band (OOB) Support
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active
      2. 9.4.2 Squelch
      3. 9.4.3 Auto Low Power
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Return Current and Plane References
      2. 12.1.2 Split Planes - What to Avoid
      3. 12.1.3 Avoiding Crosstalk
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DRF Package
8-Pin WSON
Top View
SN75LVCP600 po_llse63.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
HIGH SPEED DIFFERENTIAL I/O
RX+ 2 I Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual termination resistor circuit.
RX– 3 I
TX+ 7 O Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias by dual termination resistor circuit.
TX– 6 O
CONTROL PINS
EQ 4 I Selects equalization settings per Table 1. Internally tied to GND.
DE 8 I Selects de-emphasis settings per Table 1. Internally tied to GND.
POWER
VCC 1 P Positive supply must be 3.3 V ±10%
GND 5 G Supply ground
(1) G = Ground, I = Input, O = Output, P = Power