SLLS362G SEPTEMBER   1999  – January 2016 SN65LVDS387 , SN65LVDS389 , SN65LVDS391 , SN75LVDS387 , SN75LVDS389 , SN75LVDS391

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Driver Output Voltage and Power-On Reset
      2. 10.3.2 5-V Input Tolerance
      3. 10.3.3 NC Pins
      4. 10.3.4 Unused Enable Pins
      5. 10.3.5 Driver Equivalent Schematics
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Signaling Rate vs Distance
    2. 11.2 Typical Application
      1. 11.2.1 Point-to-Point Communications
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
          1. 11.2.1.2.1 Driver Supply Voltage
          2. 11.2.1.2.2 Driver Bypass Capacitance
          3. 11.2.1.2.3 Driver Output Voltage
          4. 11.2.1.2.4 Interconnecting Media
          5. 11.2.1.2.5 PCB Transmission Lines
          6. 11.2.1.2.6 Termination Resistor
          7. 11.2.1.2.7 Driver NC Pins
        3. 11.2.1.3 Application Curve
      2. 11.2.2 Multidrop Communications
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
          1. 11.2.2.2.1 Interconnecting Media
        3. 11.2.2.3 Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
      2. 14.1.2 Other LVDS Products
    2. 14.2 Documentation Support
      1. 14.2.1 Related Information
    3. 14.3 Related Links
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Four ('391), Eight ('389), or Sixteen ('387) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Designed for Signaling Rates Up to 630 Mbps With Very Low Radiation (EMI)
  • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load
  • Propagation Delay Times Less Than 2.9 ns
  • Output Skew Is Less Than 150 ps
  • Part-to-Part Skew Is Less Than 1.5 ns
  • 35-mW Total Power Dissipation in Each Driver Operating at 200 MHz
  • Driver Is High-Impedance When Disabled or With VCC < 1.5 V
  • SN65' Version Bus-Pin ESD Protection Exceeds 15 kV
  • Packaged in Thin Shrink Small-Outline Package With 20-mil Pin Pitch
  • Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V Tolerant

2 Applications

  • Wireless Infrastructure
  • Telecom Infrastructure
  • Printer

3 Description

This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN65LVDS387 TSSOP (64) 17.00 mm × 6.10 mm
SN75LVDS387 TSSOP (38) 9.70 mm × 4.40 mm
SN65LVDS389 SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
SN75LVDS389 TSSOP (64) 17.00 mm × 6.10 mm
SN65LVDS391 TSSOP (38) 9.70 mm × 4.40 mm
SN75LVDS391 SOIC (16) 9.90 mm × 3.91 mm
TSSOP (16) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 ai_typ_ap_lls362.gif