SLLS259J November   1996  – October 2016 SN75LVDS82

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics 
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 LVDS Input Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low Power Mode
      2. 9.4.2 Test Patterns
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Signal Connectivity
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power Up Sequence
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

DGG Package
56-Pin TSSOP
Top View

Pin Functions

Pin I/O Description
Name No.
A0M, A0P 9, 10 LVDS Input LVDS Data Lane 0
A1M, A1P 11, 12 LVDS Data Lane 1
A2M, A2P 15, 16 LVDS Data Lane 2
A3M, A3P 19, 20 LVDS Data Lane 3
CLKINM, CLKINP LVDS Clock
D0 27 LVTTL Output Data Bus Output
D1 29
D2 30
D3 32
D4 33
D5 34
D6 35
D7 37
D8 38
D9 39
D10 41
D11 42
D12 43
D13 45
D14 46
D15 47
D16 49
D17 50
D18 51
D19 53
D20 54
D21 55
D22 1
D23 2
D24 3
D25 5
D26 6
D27 7
CLKOUT 26 Clock output for the data bus
SHTDN 25 Input Shutdown Mode; Active-Low
LVDSGND 8, 14, 21 Power LVDS Ground
LVDSVCC 13 LVDS Power supply 3.3 V
PLLGND 22 PLL Ground
PLLVCC 23 PLL Power supply 3.3 V
VCC 31,40, 48, 56 Digital Power supply 3.3 V
GND 4, 28, 36, 52 Digital Ground