SLLS259J November   1996  – October 2016 SN75LVDS82

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics 
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Input and Output Schematic Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 LVDS Input Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Low Power Mode
      2. 9.4.2 Test Patterns
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Signal Connectivity
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Power Up Sequence
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Decoupling Capacitor Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage(2) –0.5 4 V
VO Output voltage (Dxx terminals) –0.5 VCC + 0.5 V
VI Input voltage Any terminal except SHTDN –0.5 VCC + 0.5 V
SHTDN –0.5 5.5 V
Continuous total power dissipation See Thermal Information
TA Operating temperature 0 70 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND, unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIH High-level input voltage (SHTDN) 2 V
VIL Low-level input voltage (SHTDN) 0.8 V
|VID| Differential input voltage 0.1 0.6 V
VIC Common-mode input voltage (see Figure 11 and Figure 7) SN75LVDS82 vid_lls259.gif 2.4 - SN75LVDS82 vid_lls259.gif V
VCC – 0.8
TA Operating free-air temperature 0 70 °C

7.4 Thermal Information

THERMAL METRIC(1) SN75LVDS82 UNIT
DGG (TSSOP)
56 PINS
RθJA Junction-to-ambient thermal resistance 57.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.6 °C/W
RθJB Junction-to-board thermal resistance 26.2 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 25.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going differential input threshold voltage 100 mV
VIT– Negative-going differential input threshold voltage(2) –100 mV
VOH High-level output voltage IOH = –4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
ICC Quiescent current (average) Disabled, All inputs open 280 μA
Enabled, AnP = 1 V,
AnM = 1.4 V,
tc = 15.38 ns		 60 74 mA
Enabled, CL = 8 pF,
Grayscale pattern
(see Figure 13),
tc = 15.38 ns		 74
Enabled, CL = 8 pF,
Worst-case pattern
(see Figure 14),
tc = 15.38 ns		 107
IIH High-level input current (SHTDN) VIH = VCC ±20 μA
IIL Low-level input current (SHTDN) VIL = 0 ±20 μA
IIN Input current (LVDS input terminals A and CLKIN) 0 ≤ VI ≤ 2.4 V ±20 μA
IOZ High-impedance output current VO = 0 or VCC ±10 μA
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designed minimum, is used in this data sheet for the negative-going input voltage threshold only.

7.6 Timing Requirements

MIN MAX UNIT
tc Cycle time, input clock(1) 14.7 32.3 ns
tsu1 Setup time, input (see Figure 2) 600 ps
th1 Hold time, input (see Figure 2) 600 ps
(1) Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles.

7.7 Switching Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tsu2 Setup time, D0–D27 valid to CLKOUT↓ CL = 8 pF, See Figure 1 5 ns
th2 Hold time, CLKOUT↓ to D0–D27 valid CL = 8 pF, See Figure 1 5 ns
tRSKM Receiver input skew margin(2)(see Figure 2) tc = 15.38 ns (± 0.2%),
|Input clock jitter| < 50 ps(3) 		490 ps
td Delay time, CLKIN↑ to CLKOUT↓ (see Figure 2) tc = 15.38 ns (± 0.2%), CL = 8 pF 3.7 ns
Δtc(o) Cycle time, change in output clock period(4) tc = 15.38 + 0.75 sin (2π500E3t) ± 0.05 ns,
See Figure 15 		±80 ps
tc = 15.38 + 0.75 sin (2π3E6t) ± 0.05 ns,
See Figure 15 		±300
ten Enable time, SHTDN↑ to Dn valid See Figure 3 1 ms
tdis Disable time, SHTDN↓ to off state See Figure 4 400 ns
tt Transition time, output (10% to 90% tr or tf) CL = 8 pF 3 ns
tw Pulse duration, output clock 0.43 tc ns
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) The parameter t(RSKM) is the timing margin available to the transmitter and interconnection skews and clock jitter. It is defined by
tc/14 – tsu1/th1.
(3) |Input clock jitter| is the magnitude of the change in input clock period.
(4) Δtc(o) is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
SN75LVDS82 pm_setup_lls259.gif Figure 1. Setup and Hold Time Waveforms
SN75LVDS82 pm_rinput_lls259.gif Figure 2. Receiver Input Skew Margin and Delay Timing Waveforms
SN75LVDS82 pm_enable_lls259.gif Figure 3. Enable Time Waveforms
SN75LVDS82 pm_disable_lls259.gif Figure 4. Disable Time Waveforms

7.8 Typical Characteristics 

SN75LVDS82 tc_sup_cur_lls259.gif Figure 5. Supply Current vs Clock Frequency
SN75LVDS82 pm_com_mo_lls259.gif Figure 7. Common-Mode Input Voltage vs Differential Input Voltage
SN75LVDS82 tc_zero_lls259.gif Figure 6. Zero-to-Peak Output Jitter vs Modulation Frequency