SLLS980E June   2009  – November 2016 SN75LVDS83A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TTL Input Data
      2. 9.3.2 LVDS Output Data
    4. 9.4 Device Functional Modes
      1. 9.4.1 Input Clock Edge
      2. 9.4.2 Low Power Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Signal Connectivity
      2. 10.1.2 PCB Routing
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power Up Sequence
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Stackup
      2. 12.1.2 Power and Ground Planes
      3. 12.1.3 Traces, Vias, and Other PCB Components
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage, VCC, LVDSVCC, PLLVCC(2) –0.5 4 V
Voltage at any output terminal –0.5 VCC + 0.5 V
Voltage at any input terminal –0.5 VCC + 0.5 V
Continuous power dissipation See Dissipation Ratings
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the GND terminals.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM)(1) ±5000 V
Charged-device model (CDM)(2) ±500
Machine model (MM)(3) ±150
(1) In accordance with JEDEC Standard 22, Test Method A114-A.
(2) In accordance with JEDEC Standard 22, Test Method C101.
(3) In accordance with JEDEC Standard 22, Test Method A115-A.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
LVDSVCC LVDS output supply voltage 3 3.3 3.6 V
PLLVCC PLL analog supply voltage 3 3.3 3.6 V
Power supply noise on any VCC terminal 0.1 V
VIH High-level input voltage VCC/2 + 0.5 V
VIL Low-level input voltage VCC/2 – 0.5 V
ZL Differential load impedance 90 132 Ω
TA Operating free-air temperature –10 70 °C

7.4 Thermal Information

THERMAL METRIC(1) SN75LVDS83A UNIT
DGG (TSSOP)
56 PINS
RθJA Junction-to-ambient thermal resistance 62.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 18.5 °C/W
RθJB Junction-to-board thermal resistance 31.1 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 30.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VT Input voltage threshold RL = 100 Ω, see Figure 6 VCC/2 V
|VOD| Differential steady-state output voltage magnitude RL = 100 Ω, see Figure 6 250 450 mV
Δ|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states RL = 100 Ω, see Figure 6 1 35 mV
VOC(SS) Steady-state common-mode output voltage tR/F (Dx, CLKin) = 1 ns, see Figure 6 1.125 1.375 V
VOC(PP) Peak-to-peak common-mode output voltage tR/F (Dx, CLKin) = 1 ns, see Figure 6 100 mV
IIH High-level input current VIH = VCC 25 µA
IIL Low-level input current VIL = 0 V ±10 µA
IOS Short-circuit output current VOY = 0 V ±24 mA
VOD = 0 V ±12 mA
IOZ High-impedance state output current VO = 0 V to VCC ±20 µA
Rpdn Input pulldown integrated resistor on all inputs Dx, CLKSEL, SHTDN, CLKIN 100 kΩ
IQ Quiescent current SHTDN = VIL, disabled, all inputs at GND 2 100 µA
ICC Supply current (average) SHTDN = VIH, RL = 100 Ω (5 places), grayscale pattern (Figure 7)
VCC = 3.3 V, fCLK = 75 MHz		 52.3 62.2 mA
SHTDN = VIH, RL = 100 Ω (5 places), 50% transition density pattern (Figure 7),
VCC = 3.3 V, fCLK = 75 MHz		 53.9 67.1 mA
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 8),
VCC = 3.6 V, fCLK = 75 MHz		 65 79.3 mA
SHTDN = VIH, RL = 100 Ω (5 places), worst-case pattern (Figure 8),
fCLK = 100 MHz		 96.8 mA
CI Input capacitance 2 pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.

7.6 Dissipation Ratings

PACKAGE CIRCUIT BOARD MODEL(1) TJA ≤ 25°C DERATING FACTOR(2)
ABOVE TJA = 25°C		 TJA = 70°C
POWER RATING
DGG Low-K 1111 mW 12.3 mW/°C 555 mW
High-K 1730 mW 19 mW/°C 865 mW
(1) In accordance with the High-K and Low-K thermal metric definitions of EIA/JESD51-2.
(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

7.7 Timing Requirements

MIN MAX UNIT
tc Input clock period 10 100 ns
Input clock modulation (SSC) with modulation frequency 30 kHz 8%
with modulation frequency 50 kHz 6%
tw High-level input clock pulse width duration 0.4 × tc 0.6 × tc ns
tt Input signal transition time 3 ns
Data set up time, D0 through D27 before CLKIN (see Figure 5) 2 ns
Data hold time, D0 through D27 after CLKIN 0.8 ns

7.8 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) tC = 10 ns, |Input clock jitter| < 25 ps
(see Figure 9)(2) 		–0.1 0 0.1 ns
t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) tC = 10 ns, |Input clock jitter| < 25 ps
(see Figure 9)(2) 		1/7 tc – 0.1 1/7 tc + 0.1 ns
t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) tC = 10 ns, |Input clock jitter| < 25 ps
(see Figure 9)(2) 		2/7 tc – 0.1 2/7 tc + 0.1 ns
t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) tC = 10 ns, |Input clock jitter| < 25 ps
(see Figure 9)(2) 		3/7 tc – 0.1 3/7 tc + 0.1 ns
t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) tC = 10 ns, |Input clock jitter| < 25 ps
(see Figure 9)(2) 		4/7 tc – 0.1 4/7 tc + 0.1 ns
t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) tC = 10 ns, |Input clock jitter| < 25 ps
(see Figure 9)(2) 		5/7 tc – 0.1 5/7 tc + 0.1 ns
t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) tC = 10 ns,
|Input clock jitter| < 25 ps
(see Figure 9)(2) 		6/7 tc – 0.1 6/7 tc + 0.1 ns
tsk(o) Output skew, tn - n/7 tC Target potential adjustment after characteristic –0.1
(–0.15)		 0.1
(0.15)		 ns
tc(o) Output clock period tc ns
Δtc(o) Output clock cycle-to-cycle jitter(3) tC = 10 ns, clean reference clock
(see Figure 10) 		±40 ps
tC = 10 ns with 0.05 UI added noise modulated at 3 MHz (see Figure 10) ±44
tC = 10 ns with 0.1 UI added noise modulated at 3 MHz (see Figure 10) ±42
tw High-level output clock pulse duration 4/7 tc ns
tr/f Differential output voltage transition time
(tr or tf)		 fCLK (see Figure 6) 225 500 ps
ten Enable time, SHTDN↑ to phase lock
(Yn valid)		 fCLK = 100 MHz (see Figure 11) 6 ms
tdis Disable time, SHTDN↓ to off-state
(CLKOUT high-impedance)		 fCLK = 100 MHz (see Figure 12) 7 ns
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) |Input clock jitter| is the magnitude of the change in the input clock period.
(3) The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed over 15,000 cycles. Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value.
SN75LVDS83A load_seq_lls846.gif Figure 1. Typical SN75LVDS83A Load and Shift Sequences

7.9 Typical Characteristics

SN75LVDS83A gscale_v_clk_lls980.gif Figure 2. Average Grayscale ICC vs Clock Frequency
SN75LVDS83A typ_prbs_lls980.gif Figure 4. Typical PRBS Output Signal vs Over One Clock Period
SN75LVDS83A outjit_v_freq_lls980.gif Figure 3. Output Clock Jitter vs Input Clock Jitter