SLLSFY8 October   2024 SN75LVPE3101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8.     14
    9. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 PCIe/SATA/SATA Express Redriver Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
      3. 6.4.3 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical SATA, PCIe and SATA Express Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

SN75LVPE3101 RGE Package 24-Pin VQFN (Top View) Figure 4-1 RGE Package 24-Pin VQFN (Top View)
Table 4-1 Pin Functions
PINTYPEINTERNAL PULLUP PULLDOWNDESCRIPTION
NAMENO.
CH1_EQ12I (4-level)PU (approx 45K)
PD (approx 95K)		CH1_EQ1. Configuration pin used to control RX EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-1 for details of timing. This pin along with CH1_EQ2 allows for up to 16 equalization settings.
CH1_EQ23I (4-level)CH1_EQ2. Configuration pin used to control RX EQ level for RX1P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-1 for details of timing. This pin along with CH1_EQ1 allows for up to 16 equalization settings.
CH2_EQ116I (4-level)CH2_EQ1. Configuration pin used to control RX EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-1 for details of timing. This pin along with CH2_EQ2 allows for up to 16 equalization settings.
CH2_EQ217I (4-level)CH2_EQ2. Configuration pin used to control RX EQ level for RX2P/N. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-1 for details of timing. This pin along with CH2_EQ1 allows for up to 16 equalization settings.
EN5I (2-level)PU (approx 400K)EN. Places SN75LVPE3101 into shutdown mode when asserted low. Normal operation when pin is asserted high. When in shutdown, the receiver terminations of the device are high impedance and the TX/RX channels are disabled.
GND 6, 10, 18, 21 GND — Ground
MODE 7 I PU (approx 45 K)
PD (approx 95K)		 MODE. The state of this pin is sampled after the rising edge of EN. Connect to GND through 20kΩ resistor.
RSVD1 24 O — RSVD1. Leave the pin unconnected.
RSVD2 14 I PU (approx 400K) RSVD2. Leave the pin unconnected.
RX1N 8 90Ω Differential Input — Inverting differential high-speed input for Channel 1
RX1P 9 Noninverting differential high-speed input for Channel 1
RX2N 20 90Ω Differential Input — Inverting differential high-speed input for Channel 2
RX2P 19 Noninverting differential high-speed input for Channel 2
TEST14IPU (approx 45K)
PD (approx 95K)		TEST1. Must connect to GND directly or through 1kΩ resistor.
TEST215IPU (approx 45K)
PD (approx 95K)		TEST2. Must connect to GND directly or through 1kΩ resistor.
TX1N 23 90Ω Differential Output — Inverting differential high-speed output for Channel 1
TX1P 22 Noninverting differential high-speed output for Channel 1
TX2N 11 90Ω Differential Output — Inverting differential high-speed output for Channel 2
TX2P 12 Noninverting differential high-speed output for Channel 2
VCC1, 13Power—3.3V (±10%) supply
Thermal pad—Thermal pad. Recommend connecting to a solid ground plane.