SLLSFY8 October   2024 SN75LVPE3101

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8.     14
    9. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 PCIe/SATA/SATA Express Redriver Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
      3. 6.4.3 Active Mode
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical SATA, PCIe and SATA Express Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

  • Route RXP/N and TXP/N pairs with controlled differential impedance. The differential impedance of the high speed traces depend on the specific design. PCIe allows differential impedances ranging from 70Ω to 100Ω, with 85Ω typically recommended for Card ElectroMechanical (CEM) specification interoperability.
  • Keep away from other high speed signals.
  • In PCIe applications, maintaining polarity through the SN75LVPE3101 is not necessary. Therefore, TI recommends connecting polarity in such a way that produces the best routing.
  • Keep intra-pair routing to within 2 mils.
  • Intra-pair length matching must be near the location of mismatch.
  • Inter-pair length matching is not necessary.
  • Separate each pair at least by 3 times the signal trace width.
  • Keep the use of bends in differential traces to a minimum. When bends are used, make sure the number of left and right bends are as equal as possible and the angle of the bend ≥ 135 degrees. This minimizes any length mismatch causes by the bends; and therefore, minimize the impact bends have on EMI.
  • Route all differential pairs on the same of layer.
  • The number of vias must be kept to a minimum. TI recommends keeping the vias count to 2 or less.
  • Keep traces on layers adjacent to ground plane.
  • Do NOT route differential pairs over any plane split.
  • When using through-hole high-speed connectors, TI recommends to route differential pairs on bottom layer to minimize the stub created by the through-hole connector.
  • Adding test points causes impedance discontinuity; and therefore, negatively impact signal performance. If test points are used, place the test points in series and symmetrically. The test points must not be placed in a manner that causes a stub on the differential pair.