SLLSFY8 October   2024 SN75LVPE3101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8.     14
    9. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 PCIe/SATA/SATA Express Redriver Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
      3. 6.4.3 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical SATA, PCIe and SATA Express Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.2 Linear Equalization

With a linear equalizer, the SN75LVPE3101 can electrically shorten a particular channel allowing for longer run lengths.

SN75LVPE3101 Linear Equalizer Figure 6-1 Linear Equalizer

With a SN75LVPE3101, a longer trace can be made to have similar insertion loss as a shorter trace. For example, a long trace of X + Y inches can be made to have similar loss characteristics of a shorter trace of X inches.

The receiver equalization level for each channel is determined by the state of the CHx_EQ1 and CHx_EQ2 pins, where x = 1 or 2.

Table 6-2 EQ Configuration Options
EQ SETTING #CHx_EQ2 PIN LEVELCHx_EQ1 PIN LEVELEQ GAIN at 2.5 GHz / 4 GHz/ 5 GHz (dB)
1001.0 / 2.3 / 3.6
20R2.1 / 4.0 / 5.5
30F3.0 / 5.2 / 6.8
4014.0 / 6.4 / 8.1
5R04.6 / 7.2 / 9.0
6RR5.5 / 8.2 / 10.0
7RF6.2 / 9.0 / 10.8
8R16.9 / 9.8 / 11.6
9F07.3 / 10.2 / 11.9
10FR7.9 / 10.9 / 12.6
11FF8.4 / 11.4 / 13.1
12F19.0 / 12.0 / 13.7
13109.4 / 12.3 / 14.1
141R9.9 / 12.8 / 14.6
151F10.3 / 13.2 / 14.9
161110.7 / 13.6 / 15.3