SLLSFY8 October   2024 SN75LVPE3101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8.     14
    9. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 PCIe/SATA/SATA Express Redriver Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
      3. 6.4.3 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical SATA, PCIe and SATA Express Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER
PACTIVE_1200mV Device power consumption when all channels are active All channels enabled , VCC = 3.3V; EN = 1; 330 mW
PSHUTDOWN Shutdown power when EN = 0. VCC = 3.3V; EN = 0 0.7 mW
4-level Inputs (TEST[2:1], MODE, CH1_EQ[2:1], CH2_EQ[2:1])
VTH Threshold "0" / "R" VCC = 3.3V 0.55 V
Threshold "R" / "F" VCC = 3.3V 1.65 V
Threshold "F" / "1" VCC = 3.3V 2.8 V
IIH High-level input current VCC = 3.6V; VIN = 3.6V 20 80 µA
IIL Low-level input current VCC = 3.6V; VIN = 0V –160 –40 µA
RPU Internal pullup resistance 45 kΩ
RPD Internal pulldown resistance 95 kΩ
EN, RSVD2
VIH High-level input voltage VCC = 3.3V 1.7 3.6 V
VIL Low-level input voltage VCC = 3.3V 0 0.7 V
IIH High-level input current VCC = 3.6V; VIN = 3.6V –10 10 µA
IIL Low-level input current VCC = 3.6V; VIN = 0V –15 15 µA
RPU_EN Internal pullup resistance for EN and RSVD2 400 kΩ
High-Speed Receiver Interface (RX1P/N and RX2P/N)
RL_100 MHz RX Differential return loss at 100MHz to 2.5GHz SDD11, 100MHz to 2.5GHz –18 dB
RL_5 GHz RX Differential return loss at 5GHz SDD11, 5GHz –14 dB
RL_10 GHz RX Differential return loss from 5GHz to 10GHz SDD11, 5GHz to 10GHz –6 dB
RL_CM RX common-mode return loss SCC11, 0.5GHz to 5GHz –12 dB
X-Talk Differential crosstalk between TX and RX signal pairs –50 dB
EACGAIN_4 GHz Maximum AC equalization gain 50mVpp CP10 at 4GHz; VCC = 3.3V 14 dB
EACGAIN_5 GHz Maximum AC equalization gain 50mVpp CP10 at 5GHz; VCC = 3.3V 16 dB
EDC_GAIN0 DC gain at 0dB setting 200mVpp VID at 100MHz 0.7 dB
VDIFF_IN Input differential peak-peak voltage swing range 1200 mV
VRX-DC-CM RX DC common-mode voltage 0 V
RRX-DC-CM RX DC common-mode impedance Measured at connector; Present when far-end termination is detected on TXP/N 18 30 Ω
RRX-DC-DIFF RX DC differential impedance Measured at connector; Present when far-end termination is detected on TXP/N 72 120 Ω
ZRX-DC-DIFF DC Input CM Input Impedance V > 0 during RESET or power down. 1. RX DC CM Impedance with RX terminations not powered. 2. Measured over the range 0mV to 500mV with respect to GND. 3. Only DC input CM Input impedance V > 0 is specified. 35 kΩ
VRX-SIGNAL-DET Input differential peak-to-peak signal detect assert level At 10Gbps; No loss input channel and PRBS7 pattern. 85 mV
VRX-IDLE-DET Input differential peak-to-peak signal detect deassert level At 10Gbps; No loss input channel and PRBS7 pattern. 60 mV
VRX-CM-AC-P Peak RX AC common-mode voltage Measured at package pin. 150 mV
High-Speed Transmitter Interface (TX1P/N and TX2P/N)
RL_TX_100 MHz TX Differential return loss at 100MHz to 2.5GHz SDD22, 100MHz to 2.5GHz –20 dB
RL_TX_2.5 GHz TX Differential return loss at 5GHz SDD22, 5GHz –16 dB
RL_TX_10 GHz TX Differential return loss from 5GHz to 10GHz SDD22, 5GHz to 10GHz –8.5 dB
RL_TX_CM TX common-mode return loss SCC22, 0.5GHz to 5 GHz –6.7 dB
VTX-DIFFPP-1200 Differential peak-to-peak TX voltage swing linear dynamic range at 100MHz 100MHz;  Measured at –1dB compression point = 20 × log(VOD/VOD_linear) 1000 mV
Differential peak-to-peak TX voltage swing linear dynamic range at 5GHz 5GHz; Measured at –1dB compression point = 20 × log(VOD/VOD_linear) 1300 mV
VTX-RCV-DETECT Amount of voltage change allowed during RX Detection. Measured at package pins. 600 mV
VTX-DC-CM TX DC common-mode voltage 0 1.85 2.05 V
VTX-CM-AC-PP-ACTIVE Transmitter AC common mode peak-peak voltage when active. Maximum mismatch from TXP+TXN for both time and amplitude. CHx_EQ setting matches input channel insertion loss 116 mV
VTX-IDLE-DIFF-AC-PP AC electrical idle differential peak-to-peak output voltage 0 10 mV
RTX-DC-CM TX DC common-mode impedance 18 30 Ω
RTX-DC-DIFF TX DC differential impedance 72 120 Ω
ITX-SHORT Transmitter short-circuit current limit. 107 mA
CAC-COUPLING External AC-coupling capacitor on differential pairs. 75 265 nF