SLLSFY8 October   2024 SN75LVPE3101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8.     14
    9. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 PCIe/SATA/SATA Express Redriver Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
      2. 6.4.2 Disconnect Mode
      3. 6.4.3 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical SATA, PCIe and SATA Express Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Switching Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tDIFF_DLY Differential propagation delay VCC = 3.0V; EN = 1 150 ps
tPWRUP_ACTIVE Time from assertion of EN to device active and performing Rx. Detect on both ports VCC = 3.0V; EN = 1 8 ms
tTX_RISE_FALL Transmitter rise/fall time VCC = 3.3V; EN = 1; 10Gbps; 20% to 80% of differential output; 1200mVpp linear range setting; Fast Input rise/fall time 27 ps
tRF_MISMATCH Transmitter rise/fall mismatch VCC = 3.3V; EN = 1; 10Gbps; 20% to 80% of differential output; 1200mVpp linear range setting; 1000mVpp VID 0.6 ps
tTX_DJ Transmitter residual deterministic jitter VCC = 3.3V; EN = 1; 10Gbps; 1200mVpp linear range setting;  Input channel loss of 12dB; Output channel loss of 1.5dB; Optimized EQ 0.05 UI