SNLS666 January   2020 SN75LVPE4410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Linear Equalization

The SN75LVPE4410 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. Table 1 shows available equalization boost through EQ0_ADDR0 and EQ1_ADDR1 control pins, when in Pin Control mode (EN_SMB = L0).

Table 1. Equalization Control Settings

EQUALIZATION SETTING TYPICAL EQ BOOST
INDEX EQ1_ADDR1 EQ0_ADDR0 @ 4 GHz @ 8 GHz
0 L0 L0 –0.3 –0.8
1 L0 L1 0.4 1.3
2 L0 L2 3.3 5.7
3 L0 L3 3.8 7.1
4 L1 L0 4.9 8.4
5 L1 L1 5.2 9.1
6 L1 L2 5.4 9.8
7 L1 L3 6.5 10.7
8 L2 L0 6.7 11.3
9 L2 L1 7.7 12.6
10 L2 L2 8.7 13.6
11 L2 L3 9.1 14.4
12 L3 L0 9.4 15.0
13 L3 L1 10.3 15.9
14 L3 L2 10.6 16.5
15 L3 L3 11.8 17.8

The equalization of the device can also be set by writing to SMBus/I2C registers in slave mode. Refer to the SN75LVPE4410 Programming Guide (SNLU270) for details.