SNLS666 January   2020 SN75LVPE4410

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3 Receiver Detect State Machine

The SN75LVPE4410 deploys an RX detect state machine that governs the RX detection cycle as defined in the PCI express specifications. At power up, after a manually triggered event through PWDN1 and PWDN2 pins (in pin mode), or writing to the relevant I2C / SMBus register, the redriver determines whether or not a valid PCI express termination is present at the far end of the link. The RX_DET pin of SN75LVPE4410 provides additional flexibility for system designers to appropriately set the device in desired mode according to Table 3.

If all four channels of SN75LVPE4410 are used for same PCI express link, the PRWDN1 and PWDN2 pin can be shorted and driven together.

Table 3. Receiver Detect State Machine Settings

PWDN1 and PWDN2 RXDET COMMENTS
L L0 PCI Express RX detection state machine is enabled. RX detection is asserted after 2x valid detections.
Pre Detect: Hi-Z, Post Detect: 50 Ω.
L L1 PCI Express RX detection state machine is enabled. RX detection is asserted after 3x valid detections.
Pre Detect: Hi-Z, Post Detect: 50 Ω.
L L2 (Float) PCI Express RX detection state machine is enabled. RX detection is asserted after 1x valid detection.
Pre Detect: Hi-Z, Post Detect: 50 Ω.
L L3 PCI Express RX detection state machine is disabled.
Recommended for non PCI Express interface use case where the SN75LVPE4410 is used as buffer with equalization.
Always 50 Ω.
H X Manual reset, input is high impedance.