SNLS693B December   2021  – December 2023 SN75LVPE5412

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Five-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
      4. 6.3.4 Receiver Detect State Machine
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Active Buffer Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 PCIe x8 Lane Switching
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
      2. 7.2.2 Protocol Agnostic Linear Redriver for High Speed Interfaces
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RUA|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 High Speed Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver
RLRX-DIFF Input differential return loss 50 MHz to 1.25GHz -22 dB
1.25GHz to 2.5GHz -22 dB
2.5GHz to 4.0GHz -20 dB
4.0GHz to 8.0GHz -13 dB
8.0GHz to 16GHz  -9 dB
RLRX-CM Input common-mode return loss 50 MHz to 2.5GHz -20 dB
2.5GHz to 8.0GHz -14 dB
8.0GHz to 16GHz -9 dB
XTRX Receive-side pair-to-pair isolation Minimum over 10 MHz to 16GHz range  -45 dB
Transmitter
VTX-AC-CM-PP Tx AC peak-to-peak common mode voltage Measured with lowest EQ, GAIN = L4; PRBS-7, 32Gbps, over at least 106 bits using a bandpass filter from 30 kHz to 500 MHz 50 mVpp
VTX-RCV-DETECT Amount of voltage change allowed during receiver detection Measured while Tx is sensing whether a low-impedance receiver is present. No load is connected to the driver output 0 600 mV
RLTX-DIFF Output differential return loss 50 MHz to 1.25GHz -22 dB
1.25GHz to 2.5GHz -22 dB
2.5GHz to 4.0GHz -21 dB
4.0GHz to 8.0GHz -15 dB
8.0GHz to 16GHz  -10 dB
RLTX-CM Output common-mode return loss 50 MHz to 2.5GHz -16 dB
2.5GHz to 8.0GHz  -12 dB
8.0GHz to 16GHz -10 dB
XTTX Transmit-side pair-to-pair isolation; port A or port B Minimum over 10 MHz to 16GHz range -50 dB
Device Datapath
TPLHD/PHLD Input-to-output latency (propagation delay) through a data channel For either low-to-high or high-to-low transition. 90 130 ps
LTX-SKEW Lane-to-lane output skew Between any two lanes within a single transmitter.  20 ps
TRJ-DATA Additive random jitter with data Jitter through redriver minus the calibration trace. 32Gbps PRBS15. 800 mVpp-diff input swing. 55 fs
TRJ-INTRINSIC Intrinsic additive random jitter with clock  Jitter through redriver minus the calibration trace. 32GHz clock. 800 mVpp-diff input swing. 35 fs
JITTERTOTAL-DATA Additive total jitter with data Jitter through redriver minus the calibration trace. 32Gbps PRBS15. 800 mVpp-diff input swing. 1.0 ps
JITTERTOTAL-INTRINSIC Intrinsic additive total jitter with clock Jitter through redriver minus the calibration trace. 16GHz clock. 800 mVpp-diff input swing. 0.1 ps
FLAT-GAIN Broadband DC and AC flat gain - input to output,  measured at DC Minimum EQ, GAIN1/0=L0  -5.6 dB
Minimum EQ, GAIN1/0=L1  -3.8 dB
Minimum EQ, GAIN1/0=L2  -1.2 dB
Minimum EQ, GAIN1/0=L3  2.6 dB
Minimum EQ, GAIN1/0=L4 (Float)  0.6 dB
EQ-MAX16G EQ boost at max setting (EQ INDEX = 19) AC gain at 16GHz relative to gain at 100 MHz. 24.0 dB
LINEARITY-DC Output DC linearity.  at 0dB flat gain 1700 mVpp
LINEARITY-AC Output AC linearity at 32Gbps at 0dB flat gain 930 mVpp