SLASF30 January   2022 TAA5212

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digial Microphone Interface
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Serial Interfaces
        1. 8.3.2.1 Control Serial Interfaces
        2. 8.3.2.2 Audio Serial Interfaces
          1. 8.3.2.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.2.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.2.2.3 Left-Justified (LJ) Interface
        3. 8.3.2.3 Using Multiple Devices With Shared Buses
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Programmable Microphone Bias
      7. 8.3.7 Signal-Chain Processing
        1. 8.3.7.1 ADC Signal-Chain
          1. 8.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 8.3.7.1.2 Programmable Channel Gain Calibration
          3. 8.3.7.1.3 Programmable Channel Phase Calibration
          4. 8.3.7.1.4 Programmable Digital High-Pass Filter
          5. 8.3.7.1.5 Programmable Digital Biquad Filters
          6. 8.3.7.1.6 Programmable Channel Summer and Digital Mixer
          7. 8.3.7.1.7 Configurable Digital Decimation Filters
            1. 8.3.7.1.7.1 Linear Phase Filters
              1. 8.3.7.1.7.1.1 Sampling Rate: 16 kHz or 14.7 kHz
              2. 8.3.7.1.7.1.2 Sampling Rate: 24 kHz or 22.05 kHz
              3. 8.3.7.1.7.1.3 Sampling Rate: 32 kHz or 29.4 kHz
              4. 8.3.7.1.7.1.4 Sampling Rate: 48 kHz or 44.1 kHz
              5. 8.3.7.1.7.1.5 Sampling Rate: 96 kHz or 88.2 kHz
      8. 8.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 8.3.9 Programmable Channel Phase Calibration
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 VEGA Registers
      2. 8.5.2 TAA5212 Registers
      3. 8.5.3 TAA5212 Registers
    6. 8.6 Feature Description
    7. 8.7 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 What to Do and What Not to Do
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-20230613-SS0I-CHDX-GQXK-PM8BMGWZ1HBS-low.svg Figure 5-1 28-Pin QFN With Exposed Thermal Pad, Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
DREG 1 Digital Supply Digital on-chip regulator output voltage for digital supply (1.5 V, nominal)
BCLK 2 Digital I/O Audio serial data interface bus bit clock
FSYNC 3 Digital I/O Audio serial data interface bus frame synchronization signal
DOUT 4 Digital I/O Audio serial data interface bus output
DIN 5 Digital Input Audio serial data interface bus input
IOVDD 6 Digital Supply Digital I/O power supply (1.8 V or 3.3 V, nominal)
VSS A2 Ground Ground Pin. Short directly to board Ground Plane.
SCL 7 Digital Input Clock for I2C Control Interface
SDA 8 Digital Input Data for I2C Control Interface
GPIO1 9 Digital I/O General-purpose digital input/output 0 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth)
GPIO2 10 Digital I/O General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth)
GPO1 11 Digital Output General-purpose digital output 1 (multipurpose functions such as audio data output, interrupt, and so forth)
GPI1 12 Digital Input General-purpose digital input 1 (multipurpose functions such as daisy-chain input, PLL input clock source, and so forth)
VSS A3 Ground Ground Pin. Short directly to board Ground Plane.
ADDR 13 Analog Input I2C Address
MICBIAS 14 Analog MICBIAS Output (Programmable output upto 3V)
IN1P 15 Analog Input Analog Input 1P Pin
IN1M 16 Analog Input Analog Input 1M Pin
IN2P 17 Analog Input Analog Input 2P Pin
IN2M 18 Analog Input Analog Input 2M Pin
VSS A4 Ground Ground Pin. Short directly to board Ground Plane.
VSSA 19 Ground Ground Pin. Short directly to board Ground Plane.
VSSA 20 Ground Ground Pin. Short directly to board Ground Plane.
VSSA 21 Ground Ground Pin. Short directly to board Ground Plane.
VSSA 22 Ground Ground Pin. Short directly to board Ground Plane.
AVDD 23 Analog Supply Analog power (3.3 V, nominal)
VREF 24 Analog Analog reference voltage filter output
VSS A1 Ground Ground Pin. Short directly to board Ground Plane.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.